Nanoscale interconnect array for stacked dies

1. A method of fabricating a microelectronic assembly, comprising:

forming an insulating layer comprising a diblock copolymer on a substrate, the insulating layer including a self-assembled nanoscale matrix array of a first polymer and a second polymer;

removing the second polymer from the nanoscale matrix array to reveal a plurality of nanoscale holes in the nanoscale matrix array;

filling the plurality of nanoscale holes with one or more conductive materials to form a plurality of nanoscale conductors within the insulating layer, the nanoscale conductors extending from a first surface of the insulating layer to a second surface of the insulating layer opposite the first surface;

joining the array of nanoscale conductors within the insulating layer to a plurality of first element contacts at a first face of a first microelectronic element, the plurality of first element contacts facing the first surface of the insulating layer;

removing the substrate from the second surface of the insulating layer;

joining the array of nanoscale conductors within the insulating layer to a plurality of second element contacts at a second face of a second microelectronic element, the plurality of second element contacts facing the second surface of the insulating layer; and

forming electrical interconnections between the first element contacts of the first microelectronic element and the second element contacts of the second microelectronic element with the plurality of nanoscale conductors, wherein the plurality of nanoscale conductors are arranged without regard to a specific alignment of the plurality of nanoscale conductors to either the plurality of first element contacts or the plurality of second element contacts.

2. The method of claim 1 , further comprising exposing the diblock copolymer to ultra-violet radiation, dissolving the second polymer, and chemically removing the second polymer to reveal the plurality of nanoscale holes.

3. The method of claim 1 , further comprising filling the plurality of nanoscale holes in the nanoscale matrix array with one or more conductive materials using electroless deposition in solution or vapor phase, or using a pulsed electrodeposition.

4. The method of claim 1 , further comprising chemically growing the plurality of nanoscale conductors within the plurality of nanoscale holes in the nanoscale matrix array in a solution, using catalyst metallic particles as seeds to grow the nanoscale conductors or using a metallic layer or metallic substrate as a seed.

5. The method of claim 1 , further comprising forming the diblock polymer insulating layer on a semiconductor wafer and transferring the insulating layer to a metallic substrate to form the array of nanoscale conductors.

6. The method of claim 1 , further comprising forming the plurality of nanoscale conductors to include multiple segments along a length of each nanoscale conductor, wherein adjacent segments of the multiple segments comprise a different conductive material.

7. The method of claim 6 , further comprising forming a segment of each nanoscale conductor nearest to the first or second surface of the insulating layer to comprise a solder or solder-type material.

8. A method of fabricating a microelectronic assembly, comprising:

forming an array of nanoscale conductors within an insulating layer on a substrate, the nanoscale conductors extending from a first surface of the insulating layer to a second surface of the insulating layer opposite the first surface, the array having a nanoscale pitch;

joining the array of nanoscale conductors within the insulating layer to a plurality of first element contacts at a first face of a first microelectronic element, the plurality of first element contacts facing the first surface of the insulating layer;

removing the substrate from the second surface of the insulating layer;

joining the array of nanoscale conductors within the insulating layer to a plurality of second element contacts at a second face of a second microelectronic element, the plurality of second element contacts facing the second surface of the insulating layer; and

forming electrical interconnections between the first element contacts of the first microelectronic element and the second element contacts of the second microelectronic element with the plurality of nanoscale conductors, wherein the nanoscale conductors of the array of nanoscale conductors are arranged without regard to a specific alignment of the nanoscale conductors to either the plurality of first element contacts or the plurality of second element contacts.

9. The method of claim 8 , further comprising forming the nanoscale conductors of a first material and coating the nanoscale conductors with a second material to obtain desired properties, wherein at least the first material or the second material is an electrically conductive material.

10. The method of claim 9 , wherein the other of the first material and the second material is an electrically non-conductive material.

11. The method of claim 8 , further comprising applying the entire array of nanoscale conductors and the insulating layer in a single application to the first microelectronic element without regard to a specific alignment of the nanoscale conductors to the first element contacts.

12. The method of claim 8 , further comprising bonding the second microelectronic element to the array of nanoscale conductors within the insulating layer without regard to a specific alignment of the nanoscale conductors to the second microelectronic element.

13. The method of claim 8 , further comprising mechanically coupling the first microelectronic element to the second microelectronic element with the insulating layer, the insulating layer comprising an adhesive.

14. The method of claim 9 , wherein at least a subset of the nanoscale conductors each comprise a non-conductive material coated with a conductive material adapted to electrically couple element contacts of the first microelectronic element to element contacts of the second microelectronic element.

15. The method of claim 8 , wherein the array of nanoscale conductors comprises a first array of nanoscale conductors, and further comprising:

joining a second array of nanoscale conductors having a nanoscale pitch within a second insulating layer to a plurality of third element contacts at a second face of the first microelectronic element, the plurality of third element contacts facing away from the first array of nanoscale conductors;

joining the second array of nanoscale conductors within the second insulating layer to a plurality of fourth element contacts at a first face of a third microelectronic element, the plurality of fourth element contacts facing the third element contacts at the second face of the first microelectronic element; and

forming electrical interconnections between the third element contacts of the first microelectronic element and the fourth element contacts of the third microelectronic element with the second array of nanoscale conductors, wherein the nanoscale conductors of the second array of nanoscale conductors are arranged without regard to a specific alignment of the nanoscale conductors to either the plurality of third element contacts or the plurality of fourth element contacts.

16. The method of claim 15 , further comprising mechanically coupling the third microelectronic element to the first microelectronic element using the second insulating layer, which comprises an adhesive polymer.

17. The method of claim 15 , further comprising forming a three-dimensional stack by joining one or more additional microelectronic elements to the second microelectronic element and/or the third microelectronic element, an additional array of nanoscale conductors within an additional insulating layer disposed between adjacent microelectronic elements of the stack, the array of nanoscale conductors forming an electrical interconnection between contact terminals of the adjacent microelectronic elements of the stack.

18. The method as claimed in claim 17 , wherein a first pair of adjacent microelectronic elements includes a different arrangement of contact terminals than a second pair of adjacent microelectronic elements, and wherein an array of nanoscale conductors disposed between the first pair of adjacent microelectronic elements and another array of nanoscale conductors disposed between the second pair of adjacent microelectronic elements have a same physical arrangement of nanoscale conductors.

19. The method of claim 8 , wherein a pitch of the plurality of first element contacts or the plurality of second element contacts is at least one micrometer, and wherein a pitch of each of the plurality of nanoscale conductors is less than the pitch of any of the plurality of first element contacts or the plurality of second element contacts.