Warpage balancing in thin packages

1. A method of fabricating a microelectronic assembly, comprising:

forming a plurality of electrical contacts on a second surface of a carrier or a package, the carrier or package having a first surface arranged to receive a microelectronic component and a second surface opposite the first surface;

forming a plurality of solder balls on the plurality of electrical contacts;

deforming each solder ball of the plurality of solder balls;

forming a reinforcement layer on the second surface of the carrier or the package to add structural support to the carrier or the package, the reinforcement layer surrounding each solder ball;

reflowing the plurality of solder balls to partially or completely detach each solder ball from the reinforcement layer.

2. The method of claim 1 , further comprising pressing on the solder balls with a tool to change a shape of the solder balls prior to forming the reinforcement layer.

3. The method of claim 1 , further comprising removing a portion of each solder ball by grinding or shaving to deform the solder balls.

4. The method of claim 1 , further comprising forming an opening in the reinforcement layer around each solder ball, the opening having a truncated ovoid shape.

5. The method of claim 1 , further comprising forming the reinforcement layer on the second surface of the carrier or the package without the use of a solder resist mask or an adhesive layer.

6. The method of claim 1 , further comprising reducing a mechanical stress between the solder balls and the reinforcement layer by at least partially decoupling the solder balls from the reinforcement layer, the decoupling allowing the solder balls to expand or change a position during later processing.

7. The method of claim 1 , further comprising selecting a reinforcement layer material having a coefficient of thermal expansion (CTE) that counter balances a warpage tendency of the carrier or the package.

8. The method of claim 7 , wherein the CTE of the reinforcement layer material is less than a CTE of a material of the carrier or the package.

9. A method of fabricating a microelectronic assembly, comprising:

forming a plurality of electrical contacts on a second surface of a carrier or a package, the carrier or package having a first surface arranged to receive a microelectronic component and a second surface opposite the first surface;

forming a reinforcement layer on the second surface of the carrier or the package to add structural support to the carrier or the package, the reinforcement layer including one or more openings to reveal the electrical contacts; and

forming a plurality of solder balls on the plurality of electrical contacts and within the one or more openings, the solder balls making partial contact or no contact with the reinforcement layer and having space with respect to the reinforcement layer to change position and change shape when used to electrically couple the carrier or the package to a second carrier or a second package.

10. The method of claim 9 , further comprising forming the reinforcement layer on the second surface of the carrier or the package without the use of a solder resist mask or an adhesive layer.

11. The method of claim 9 , further comprising forming the reinforcement layer using a material having a coefficient of thermal expansion (CTE) less than 12.

12. The method of claim 9 , further comprising forming the one or more openings in the reinforcement layer prior to attaching the reinforcement layer to the second surface of the carrier or the package.

13. The method of claim 9 , further comprising forming the one or more openings in the reinforcement layer after attaching the reinforcement layer to the second surface of the carrier or the package.

14. The method of claim 9 , further comprising filling the one or more openings with solder, and reflowing to form the plurality of solder balls and to partially or completely decouple the solder balls from the reinforcement layer.

15. The method of claim 9 , further comprising forming the reinforcement layer on the second surface of the carrier or the package after a die or a package is coupled to the first surface of the carrier or the package.

16. A microelectronic structure, comprising:

a carrier or a package having a first surface and a second surface opposite the first surface;

a plurality of electrical contacts disposed on the second surface of the carrier or the package;

a reinforcement layer disposed on the second surface of the carrier or the package, the reinforcement layer including one or more openings to reveal the electrical contacts, the reinforcement layer arranged to add structural support to the carrier or the package; and

a plurality of solder balls disposed within the one or more openings and coupled to the electrical contacts, the solder balls making partial contact or no contact with the reinforcement layer and having space with respect to the reinforcement layer to change position and change shape when used to electrically couple the carrier or the package to a second carrier or a second package.

17. The microelectronic structure of claim 16 , further comprising one or more groups of solder balls within each of the one or more openings.

18. The microelectronic structure of claim 16 , wherein the reinforcement layer is attached directly to the second surface of the carrier or the package without the use of a solder resist mask or an adhesive.

19. The microelectronic structure of claim 16 , wherein a coefficient of thermal expansion (CTE) of the reinforcement layer is within 20% of an effective CTE of components attached to the first surface of the carrier, including a chip die, a plurality of interconnects, an underfill material, and a package encapsulant.

20. The microelectronic structure of claim 16 , wherein the one or more openings in the reinforcement layer are drilled prior to attaching the reinforcement layer to the second surface of the carrier or the package.