Semiconductor chip package with post electrodes
View Patent ↗A first wiring pattern is formed on a surface of a first support plate; a semiconductor chip is disposed on the first wiring pattern; and electrode terminals of the semiconductor chip are electrically connected to the first wiring pattern at required positions. Post electrodes connected to a second wiring pattern of a wiring-added post electrode component integrally connected by a second support plate are collectively fixed and electrically connected to the first wiring pattern formed on the first support plate at predetermined positions. After sealing with resin, the first and second support plates are separated; a glass substrate is affixed on a front face side; and external electrodes connected to the second wiring pattern are formed on a back face side.
1. A semiconductor chip package in which a substrate provided on a front face side, a semiconductor chip mounted on the substrate, and external electrodes located on a back face side opposite the substrate and connected to the semiconductor chip are integrally packaged,
wherein the substrate has a first wiring pattern formed on a surface thereof; the semiconductor chip is disposed on the first wiring pattern; and electrode terminals of the semiconductor chip are electrically connected to the first wiring pattern at required positions;
post electrodes connected to a second wiring pattern of a wiring-added post electrode component integrally connected by an insulation tape affixed to the entire surface of a support plate are connected to the first wiring pattern formed on the substrate at predetermined positions; and
holes are formed in the insulation tape on the back face side from which the support plate has been separated; and the external electrodes connected to the second wiring pattern exposed through openings of the holes are formed.
2. A semiconductor chip package according to claim 1 , wherein the substrate is a glass substrate or a light-transmissive transparent resin substrate, or a highly heat-releasing substrate which functions as a heat sink.
3. A semiconductor chip package in which a substrate provided on a front face side, a semiconductor chip mounted on the substrate, and external electrodes located on a back face side opposite the substrate and connected to the semiconductor chip are integrally packaged,
wherein the substrate is affixed to a position from which a first support plate has been separated; the first support plate has a first wiring pattern formed on a surface thereof; the semiconductor chip is disposed on the first wiring pattern; and electrode terminals of the semiconductor chip are electrically connected to the first wiring pattern at required positions;
post electrodes connected to a second wiring pattern of a wiring-added post electrode component integrally connected by an insulation tape affixed to the entire surface of a second support plate are connected to the first wiring pattern formed on the first support plate at predetermined positions; and
holes are formed in the insulation tape on the back face side from which the second support plate has been separated; and the external electrodes connected to the second wiring pattern exposed through openings of the holes are formed.
4. A semiconductor chip package according to claim 3 , wherein the substrate is a glass substrate or a light-transmissive transparent resin substrate, or a highly heat-releasing substrate which functions as a heat sink.
5. A method of manufacturing a semiconductor chip package in which a substrate provided on a front face side, a semiconductor chip mounted on the substrate, and external electrodes located on a back face side opposite the substrate and connected to the semiconductor chip are integrally packaged, comprising:
forming a first wiring pattern on a surface of a first support plate; disposing the semiconductor chip on the first wiring pattern; and electrically connecting electrode terminals of the semiconductor chip to the first wiring pattern at required positions;
collectively fixing and electrically connecting post electrodes connected to a second wiring pattern of a wiring-added post electrode component integrally connected by a second support plate, to the first wiring pattern formed on the first support plate at predetermined positions; and
after sealing with resin, separating the first and second support plates, affixing the substrate on the front face side, and forming the external electrodes connected to the second wiring pattern on the back face side.
6. A method of manufacturing a semiconductor chip package according to claim 5 , wherein the substrate is a glass substrate or a light-transmissive transparent resin substrate, or a highly heat-releasing substrate which functions as a heat sink.
7. A method of manufacturing a semiconductor chip package in which a substrate provided on a front face side, a semiconductor chip mounted on the substrate, and external electrodes located on a back face side opposite the substrate and connected to the semiconductor chip are integrally packaged, comprising:
forming a first wiring pattern on a surface of the substrate; disposing the semiconductor chip on the first wiring pattern; and electrically connecting electrode terminals of the semiconductor chip to the first wiring pattern at required positions;
collectively fixing and electrically connecting post electrodes connected to a second wiring pattern of a wiring-added post electrode component integrally connected by a support plate, to the first wiring pattern formed on the substrate at predetermined positions; and
after sealing with resin, separating the support plate, and forming the external electrodes connected to the second wiring pattern on the back face side.
8. A method of manufacturing a semiconductor chip package according to claim 7 , wherein the substrate is a glass substrate or a light-transmissive transparent resin substrate, or a highly heat-releasing substrate which functions as a heat sink.
9. A method of manufacturing a semiconductor chip package according to claim 7 , wherein an insulation tape which functions as a protection film is affixed to the entire surface of the support plate of the wiring-added post electrode component.
10. A method of manufacturing a semiconductor chip package in which a substrate provided on a front face side, a semiconductor chip mounted on the substrate, and external electrodes located on a back face side opposite the substrate and connected to the semiconductor chip are integrally packaged, comprising:
forming a first wiring pattern on a surface of a first support plate; disposing the semiconductor chip on the first wiring pattern; and electrically connecting electrode terminals of the semiconductor chip to the first wiring pattern at required positions;
collectively fixing and electrically connecting post electrodes connected to a second wiring pattern of a wiring-added post electrode component integrally connected by an insulation tape affixed to the entire surface of a second support plate, to the first wiring pattern formed on the first support plate at predetermined positions; and
after sealing with resin, separating the first and second support plates, affixing the substrate on the front face side, and, on the back face side, forming holes in the insulation tape and forming the external electrodes connected to the second wiring pattern exposed through openings of the holes.
11. A method of manufacturing a semiconductor chip package according to claim 10 , wherein the substrate is a glass substrate or a light-transmissive transparent resin substrate, or a highly heat-releasing substrate which functions as a heat sink.
12. A method of manufacturing a semiconductor chip package in which a substrate provided on one side, a semiconductor chip mounted on the substrate, and external electrodes located on a side opposite the substrate and connected to the semiconductor chip are integrally packaged, comprising:
forming post electrodes supported by a support plate, and wiring connected to the post electrodes so as to form a wiring-added post electrode component having an upper-face wiring pattern formed thereon,
mounting the semiconductor chip on the wiring-added post electrode component and sealing the semiconductor chip with resin,
separating the support plate and affixing the substrate to a position from which the support plate has been separated, and
using ends of the post electrodes exposed from a surface of the resin seal as the external electrodes or forming the external electrodes on the surface of the resin seal.
13. A method of manufacturing a semiconductor chip package according to claim 12 , wherein the semiconductor chip is an image sensor chip, or a high-power LSI chip which requires intensive release of heat, and the substrate is a glass substrate or a light-transmissive transparent resin substrate, or a highly heat-releasing substrate.