Network on layer enabled architectures
The technology relates to a system on chip (SoC). The SoC may include a network on layer including one or more routers and an application specific integrated circuit (ASIC) layer bonded to the network layer, the ASIC layer including one or more components. In some instances, the network layer and the ASIC layer each include an active surface and a second surface opposite the active surface. The active surface of the ASIC layer and the second surface of the network may each include one or more contacts, and the network layer may be bonded to the ASIC layer via bonds formed between the one or more contacts on the second surface of the network layer and the one or more contacts on the active surface of the ASIC layer.
1. A system on chip (SoC) comprising:
a network layer including two or more routers; and
an application specific integrated circuit (ASIC) layer bonded to the network layer, the ASIC layer including two or more components, including a first component having a first network interface and a second component having a second network interface, wherein the first component is connected to a first router of the two or more routers via the first network interface and the second component is connected to a second router of the two or more routers via the second network interface,
wherein the first router and the second router of the two or more routers are configured to route data through the network layer from the first network interface of the first component to the second network interface of the second component.
2. The system of claim 1 , wherein the two or more components include one or more of processors, graphics processing units (GPUs), logic boards, digital sound processors (DSP), or network adaptors.
3. The system of claim 1 , wherein the two or more routers of the network layer are connected via one or more routing traces in the network layer.
4. The system of claim 1 , wherein the two or more routers are arranged in a mesh pattern, a ring pattern, or a star pattern.
5. The system of claim 1 , wherein the network layer is connected to memory located outside of the SoC.
6. The system of claim 1 , wherein the network layer and the ASIC layer each includes:
an active surface; and
a second surface opposite the active surface.
7. The system of claim 6 , wherein the second surface of the ASIC layer includes one or more terminals.
8. The system of claim 6 , wherein the active surface of the ASIC layer and the second surface of the network layer each includes one or more contacts,
wherein the network layer is bonded to the ASIC layer via bonds formed between the one or more contacts on the second surface of the network layer and the one or more contacts on the active surface of the ASIC layer.
9. The system of claim 8 , wherein the bonds are formed via ZiBond direct bonding and/or direct bond interconnect (DBI) hybrid bonding.
10. The system of claim 1 , further including a memory layer including an active surface including one or more contacts.
11. The system of claim 10 , wherein the memory layer is bonded to the network layer via bonds formed between one or more contacts on the active surface of the network layer and the one or more contacts on the active surface of the memory layer.
12. The system of claim 11 , wherein the bonds are formed via ZiBond direct bonding and/or direct bond interconnect (DBI) hybrid bonding.
13. The system of claim 10 , wherein each of the two or more components is connected at least one of the two or more routers in the network layer via one or more conductive structures.
14. The system of claim 13 , wherein the conductive structures include one or more of traces, vias, contacts, or terminals.
15. The system of claim 13 , wherein each of the two or more components include a network interface.
16. The system of claim 15 , wherein each of the two or more components are connected to at least one of the two or more routers through their respective network interfaces.
17. The system of claim 15 , wherein the memory layer includes one or more memory segments.
18. The system of claim 17 , wherein each of the one or more memory segments is connected to at least one of the two or more routers in the network layer via one or more conductive structures.
19. The system of claim 17 , wherein the network layer is configured to route data between the two or more components and the one or more memory segments.
20. The system of claim 17 , wherein the network layer is configured to ignore faulty memory segments or faulty processors.