Embedded wire bond wires
View Patent ↗Apparatuses relating generally to a vertically integrated microelectronic package are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface. A first microelectronic device is coupled to the upper surface of the substrate. The first microelectronic device is a passive microelectronic device. First wire bond wires are coupled to and extend away from the upper surface of the substrate. Second wire bond wires are coupled to and extend away from an upper surface of the first microelectronic device. The second wire bond wires are shorter than the first wire bond wires. A second microelectronic device is coupled to upper ends of the first wire bond wires and the second wire bond wires. The second microelectronic device is located above the first microelectronic device and at least partially overlaps the first microelectronic device.
1. A vertically integrated microelectronic package, comprising:
a substrate having an upper surface and a lower surface opposite the upper surface;
a first microelectronic device coupled to the upper surface of the substrate, the first microelectronic device being a passive microelectronic device;
first wire bond wires coupled to and extending away from the upper surface of the substrate;
second wire bond wires coupled to and extending away from an upper surface of the first microelectronic device, the second wire bond wires being shorter than the first wire bond wires;
a second microelectronic device coupled to upper ends, including corresponding tips, of the first wire bond wires and the second wire bond wires, the second microelectronic device located above the first microelectronic device and at least partially overlapping the first microelectronic device;
a molding layer having an uppermost surface and a lowermost surface opposite the uppermost surface, the molding layer disposed for surrounding portions of lengths of a first subset of the first wire bond wires and portions of lengths of second wire bond wires; wherein the upper ends of the first subset of the first wire bond wires, the upper ends of the second subset of the first wire bond wires and the upper ends of the second wire bond directly interconnect the second microelectronic device above the uppermost surface of the molding layer;
wherein the second subset of the first wire bond wires are located outside of the molding layer;
the first microelectronic device is disposed in the molding layer and completely located between the uppermost surface and the lowermost surface of the molding layer;
the second microelectronic device is coupled above the uppermost surface of the molding layer;
a third microelectronic device coupled to and located above the second microelectronic device and at least partially overlapping the second microelectronic device;
wherein the third microelectronic device is coupled above the uppermost surface of the molding layer; and
wherein both the first microelectronic device and the third microelectronic device are in a face-down orientation for facing the upper surface of the substrate.
2. The vertically integrated microelectronic package according to claim 1 , wherein the second microelectronic device is a passive microelectronic device.
3. The vertically integrated microelectronic package according to claim 1 , wherein the second microelectronic device is an active microelectronic device.
4. The vertically integrated microelectronic package according to claim 1 , wherein both the first microelectronic device and the second microelectronic device are in a face-down orientation for facing the upper surface of the substrate.
5. The vertically integrated microelectronic package according to claim 1 , wherein the second microelectronic device and the third microelectronic device are respective passive microelectronic devices.
6. The vertically integrated microelectronic package according to claim 1 , wherein the second microelectronic device and the third microelectronic device respectively are another passive microelectronic device and an active microelectronic device.
7. The vertically integrated microelectronic package according to claim 1 , wherein
the third microelectronic device is an active microelectronic device.
8. A vertically integrated microelectronic package, comprising:
a substrate having an upper surface and a lower surface opposite the upper surface;
a first microelectronic device coupled to the upper surface of the substrate, the first microelectronic device being a passive microelectronic device;
first wire bond wires coupled to and extending away from the upper surface of the substrate;
second wire bond wires coupled to and extending away from an upper surface of the first microelectronic device;
a first portion of the first wire bond wires being taller than the second wire bond wires;
a second microelectronic device coupled to first upper ends of the first portion the first wire bond wires and coupled to upper ends, including corresponding tips, of the second wire bond wires, the second microelectronic device located above the first microelectronic device and at least partially overlapping the first microelectronic device;
a second portion of the first wire bond wires having second upper ends thereof coupled to the upper surface of the first microelectronic device;
a molding layer having an uppermost surface and a lowermost surface opposite the uppermost surface disposed for surrounding lengths of both the first wire bond wires and the second wire bond wires with the first upper ends of the first portion of the first wire bond wires and the upper ends of the second wire bond wires directly interconnected to the second microelectronic device above the uppermost surface;
the first microelectronic device disposed in the molding layer and completely located between the uppermost surface and the lowermost surface of the molding layer;
the second microelectronic device coupled above the uppermost surface of the molding layer;
a third microelectronic device coupled to and located above the second microelectronic device and at least partially overlapping the second microelectronic device;
wherein the third microelectronic device is coupled above the uppermost surface of the molding layer; and
wherein both the first microelectronic device and the third microelectronic device are in a face-down orientation for facing the upper surface of the substrate.
9. The vertically integrated microelectronic package according to claim 8 , wherein the second microelectronic device and the third microelectronic device are respective passive microelectronic devices.
10. The vertically integrated microelectronic package according to claim 8 , wherein the second microelectronic device and the third microelectronic device respectively are another passive microelectronic device and an active microelectronic device.