Capacitive coupling in a direct-bonded interface for microelectronic devices
Capacitive couplings in a direct-bonded interface for microelectronic devices are provided. In an implementation, a microelectronic device includes a first die and a second die direct-bonded together at a bonding interface, a conductive interconnect between the first die and the second die formed at the bonding interface by a metal-to-metal direct bond, and a capacitive interconnect between the first die and the second die formed at the bonding interface. A direct bonding process creates a direct bond between dielectric surfaces of two dies, a direct bond between respective conductive interconnects of the two dies, and a capacitive coupling between the two dies at the bonding interface. In an implementation, a capacitive coupling of each signal line at the bonding interface comprises a dielectric material forming a capacitor at the bonding interface for each signal line. The capacitive couplings result from the same direct bonding process that creates the conductive interconnects direct-bonded together at the same bonding interface.
1. A microelectronic device comprising:
a dielectric-to-dielectric direct bond between a first die and a second die, the first die and the second die being direct-bonded together at a bonding interface;
a metal-to-metal direct bond at the bonding interface forming a conductive interconnect between the first die and the second die; and
a capacitive interconnect between the first die and the second die formed at the bonding interface,
wherein the capacitive interconnect comprises a first layer of a first dielectric medium on a first metal of the first die and a second layer of a second dielectric medium on a second metal of the second die,
wherein a spacing distance between the first metal and the second metal is selected to provide a capacitance value for the capacitive interconnect;
wherein the conductive interconnect comprises one of (i) a direct-bonded power interconnect or (ii) a direct-bonded ground interconnect, and
wherein the capacitive interconnect comprises a signal line between the first die and the second die.
2. The microelectronic device of claim 1 , wherein at least one (i) the first layer of the first dielectric medium and (ii) the second layer of the second dielectric medium is substantially flush with the bonding interface.
3. The microelectronic device of claim 1 , further comprising a layer of dielectric material between the first layer and the second layer.
4. The microelectronic device of claim 3 , wherein a combined thickness of the first layer, the second layer, and the layer of dielectric material is less than about 25 nanometers.
5. The microelectronic device of claim 1 , wherein at least one (i) the first metal of the capacitive interconnect in the first die or (ii) the second metal of the capacitive interconnect in the second die is recessed from the bonding interface.
6. The microelectronic device of claim 1 , wherein a spacing distance between the first metal in the first die and the second metal in the second die is selected to provide a capacitance value for the capacitive interconnect.
7. The microelectronic device of claim 1 , wherein the capacitive interconnect includes at least one first conductive contact below the bonding interface of the first die and at least one second conductive contact below the bonding interface of the second die, the dielectric-to-dielectric direct bond between the first die and the second die extending between the at least one first conductive contact and the at least one second conductive contact.
8. The microelectronic device of claim 7 , wherein the dielectric-to-dielectric direct bond between the first die and the second die extends between adjacent first conductive contacts and adjacent second conductive contacts.
9. A microelectronic device comprising:
a dielectric-to-dielectric direct bond between respective nonmetal surfaces of a first die and a second die, the first die and the second die being direct-bonded together at a bonding interface;
a metal-to-metal direct bond at the bonding interface forming a conductive interconnect between the first die and the second die; and
a capacitive interconnect between the first die and the second die formed at the bonding interface, the capacitive interconnect comprising a first layer of a first dielectric medium on a first metal of the first die and a second layer of a second dielectric medium on a second metal of the second die,
wherein a combined thickness of the first layer and the second layer is less than about 25 nanometers, and
wherein the capacitive interconnect comprises a signal line between the first die and the second die.
10. The microelectronic device of claim 9 , wherein the conductive interconnect comprises one of (i) a direct-bonded power interconnect or (ii) a direct-bonded ground interconnect.
11. The microelectronic device of claim 9 , wherein at least one (i) the first metal of the capacitive interconnect in the first die or (ii) the second metal of the capacitive interconnect in the second die is recessed from the bonding interface.
12. The microelectronic device of claim 9 , wherein at least one (i) the first layer of the first dielectric medium and (ii) the second layer of the second dielectric medium is substantially flush with the bonding interface.