Embedded organic interposers for high bandwidth

1. An apparatus, comprising:

a microelectronics package including a substrate having a core layer;

an organic interposer embedded in a space formed in the core layer of the substrate, the organic interposer buried beneath at least one conductive layer of the microelectronics package;

conductive traces in the organic interposer providing at least four conductive layers in the space, above a core material or a conductive layer of the core layer of the substrate;

an instance of the organic interposer coupling each of multiple high bandwidth memory (HBM) stacks with an application specific integrated circuit (ASIC) chip or with a logic chip;

for each HBM stack, the conductive traces of the organic interposer capable of interfacing with a linear interface comprising high density wiring for multiple HBM modules in the HBM stack, the conductive traces partitioning the high density wiring of the multiple HBM modules of the HBM stack into the at least four conductive layers in the space formed in the core layer of the substrate; and

the conductive traces of the organic interposer providing data transmission at a signal frequency range greater than 1 GHz.

2. The apparatus of claim 1 , wherein the conductive traces in the at least four layers have a line/space greater than at least five times a beachfront pitch of a chip or a die connected to the organic interposer, the beachfront pitch comprising a pinout density of the chip or the die.

3. The apparatus of claim 1 , wherein each conductive layer comprises a transmission line structure of the conductive traces with a tracing space of at least 3 microns (μm) or within a range of 2-10 microns, and dimensions of the conductive traces comprising a width in the range of 2-10 microns and a thickness in the range of 1-7 microns, per 5-16 mm length of each conductive layer.

4. The apparatus of claim 1 , wherein each conductive layer of the at least four conductive layers provides the bandwidth performance of greater than 1 GHz with no greater than −5 dB insertion loss per 15 mm length of the conductive layer.

5. The apparatus of claim 1 , further comprising chip capacitors embedded adjacent to the organic interposer in the core layer to increase a power integrity of the microelectronic package.

6. The apparatus of claim 1 , wherein the organic interposer further comprises at least one semiconductor core embedded in the organic interposer.

7. The apparatus of claim 1 , wherein a width dimension of the organic interposer comprises up to at least a same width as a corresponding semiconductor die, a corresponding high bandwidth memory stack, an entire row of high bandwidth memory stacks, or a high bandwidth memory component.

8. The apparatus of claim 1 , wherein the core layer of the substrate comprises:

a first core layer;

a cavity formed in the first core layer for embedding the organic interposer;

a second core layer; and

wherein the first core layer and the second core layer are laminated together to form the core layer of the microelectronics package embedding the organic interposer.

9. The apparatus of claim 1 , wherein the core layer of the substrate comprises a ceramic material with cavities or impressions formed in the ceramic substrate; and

wherein the organic interposer comprises a layer of an organic substrate applied over the ceramic material, the organic substrate inlaid in the cavities or impressions of the ceramic material.

10. The apparatus of claim 1 , wherein an instance of the organic interposer underpasses a first high bandwidth memory stack to connect to a second high bandwidth memory stack more remote from the organic interposer than the first high bandwidth memory stack, or underpasses another instance of the organic interposer to connect to the first high bandwidth memory stack or the second high bandwidth memory stack.

11. The apparatus of claim 1 , wherein an instance of the organic interposer underpasses a first row of electronic components to connect to multiple electronic components of a second row of electronic components.

12. The apparatus of claim 1 , wherein the organic interposer bends or branches in the core layer in an x-y plane, an x-z plane, or a y-z plane.

13. A microelectronics package, comprising:

a substrate comprising a core;

an organic interposer embedded in the core of the substrate, the organic interposer buried beneath at least one conductive layer of the microelectronics package;

conductive traces in the organic interposer providing at least four conductive layers in the organic interposer;

an instance of the organic interposer coupling at least a first chip with at least a second chip;

the conductive traces of the organic interposer providing data transmission at a signal frequency range greater than 1 GHz; and

wherein the organic interposer passes beneath at least one die or chip on a surface of the substrate, without connecting to the die or the chip.

14. The microelectronics package of claim 13 , wherein the organic interposer is buried beneath at least three redistribution layers (RDLs) or three successive routing layers built on a surface of the substrate.

15. The microelectronics package of claim 13 , wherein the organic interposer passes beneath the at least one die or chip without connecting to the die or the chip, while connecting two chips on either side of the at least one die or chip not connected to.

16. The microelectronics package of claim 13 , wherein the organic interposer passes beneath another instance of the organic interposer.