Region shielding within a package of a microelectronic device
A microelectronic device may include a substrate, a first chip on the substrate, and a second chip on the substrate. A plurality of pillars may be located between the first chip and the second chip, wherein a first end of each pillar of the plurality of pillars is adjacent to the substrate. A spacing among the plurality of pillars is at least equal to a distance sufficient to block electromagnetic interference (EMI) and/or radio frequency interference (RFI) between the first chip and the second chip. The microelectronic device may also include a cover over at least the first chip, the second chip, and the plurality of pillars, wherein a second end of each pillar of the plurality of pillars is at least adjacent to a trench defined within the cover. The trench may include a conductive material therein.
1. A microelectronic device comprising:
a substrate;
a first chip on the substrate and a second chip on the substrate;
a plurality of pillars between the first chip and the second chip, wherein:
a first end of individual pillars of the plurality of pillars is adjacent to the substrate;
the individual pillars of the plurality of pillars are arranged in a preselected manner for one or more frequencies associated with an interference between the first chip and the second chip; and
the plurality of pillars are positioned to substantially shield the interference at the one or more frequencies between the first chip and the second chip; and
a cover over at least the first chip, the second chip, and the plurality of pillars, wherein a second end of the individual pillars of the plurality of pillars is disposed in or adjacent to a trench defined within the cover.
2. The microelectronic device of claim 1 , wherein:
the trench is filled with a conductive material; and
the second end of the individual pillars of the plurality of pillars engages a bottom surface of the conductive material.
3. The microelectronic device of claim 2 , wherein an outer surface of the cover includes a layer of the conductive material.
4. The microelectronic device of claim 1 , wherein the cover extends to the substrate.
5. The microelectronic device of claim 1 , wherein the first end of the individual pillars of the plurality of pillars is coupled to one of (i) a conductive trace or (ii) a corresponding conductive pad of a plurality of conductive pads exposed at a surface of the substrate.
6. The microelectronic device of claim 5 , wherein the first end of the individual pillars is integral with the one of (i) the conductive trace or (ii) the corresponding conductive pad of the plurality of conductive pads.
7. The microelectronic device of claim 1 , wherein a material of the cover extends between the plurality of pillars.
8. The microelectronic device of claim 1 , wherein the individual pillars of the plurality of pillars are arranged linearly between the first chip and the second chip.
9. The microelectronic device of claim 1 , wherein a spacing between the first chip and the second chip is in a range of 100 microns and 2000 microns.
10. A microelectronic device comprising:
a substrate having a first region, a second region, and a third region between the first region and the second region, the substrate comprising (i) a surface and (ii) a ground plane;
at least one first microelectronic element overlying the surface within the first region;
at least one second microelectronic element overlying the surface within the second region;
an electrically conductive element exposed at the surface of the substrate within the third region and coupled to the ground plane;
a plurality of conductive posts within the third region having (i) first ends coupled to the electrically conductive element and (ii) second ends opposite the first ends;
a dielectric encapsulation layer extending from the surface of the substrate and filling spaces between conductive posts of the plurality of conductive posts such that the conductive posts are separated from one another by the dielectric encapsulation layer, the dielectric encapsulation layer comprising a first portion at a first height above the surface overlying the first region of the substrate, a second portion at a second height above the surface overlying the second region of the substrate, and a third portion at a third height above the surface overlying the third region of the substrate, wherein the third height is less than the first height and the second height, and wherein the second ends of the plurality of conductive posts are at least adjacent to the third portion; and
a conductive material within at least the third portion of the dielectric encapsulation layer.
11. The microelectronic device of claim 10 , wherein an interconnected combination of the ground plane, the conductive material, and the plurality of conductive posts provides a Faraday cage.
12. The microelectronic device of claim 10 , wherein the plurality of conductive posts are arranged in a preselected manner for one or more frequencies associated with an interference between the at least one first microelectronic element and the at least one second microelectronic element.
13. The microelectronic device of claim 10 , wherein the first ends of the plurality of conductive posts are coupled to the electrically conductive element.
14. The microelectronic device of claim 13 , wherein the first ends of the plurality of conductive posts are integral with the electrically conductive element.
15. The microelectronic device of claim 10 , wherein the plurality of conductive posts is arranged linearly between the at least one first microelectronic element and the at least one second microelectronic element.
16. A microelectronic device comprising:
a substrate, wherein the substrate comprises one of (i) a conductive trace or (ii) a plurality of conductive pads
a plurality of pillars, wherein:
a first end of individual pillars of the plurality of pillars is coupled to one of (i) the conductive trace or (ii) a corresponding conductive pad of the plurality of conductive pads; and
the individual pillars of the plurality of pillars are arranged in a preselected manner for one or more frequencies associated with an interference between a first chip on the substrate and a second chip on the substrate;
the first chip on the substrate, wherein the first chip is adjacent to a first side of the plurality of pillars;
the second chip on the substrate, wherein the second chip is adjacent to a second side of the plurality of pillars; and
a cover over at least the first chip, the second chip, and the plurality of pillars, wherein:
the cover comprises a trench filled with a conductive material; and
a second end of each pillar of the plurality of pillars is disposed in or adjacent to the trench.
17. The microelectronic device of claim 16 , wherein the first end of the individual pillars is integral with the one of (i) the conductive trace or (ii) the corresponding conductive pad of a plurality of conductive pads.
18. The microelectronic device of claim 16 , wherein the cover comprises an epoxy molding compound.
19. The microelectronic device of claim 16 , wherein a spacing between the first chip and the second chip is in a range of 100 microns and 2000 microns.