Systems and methods for flash stacking
A three-dimensional stacking technique performed in a wafer-to-wafer fashion reducing the machine movement in production. The wafers are processed with metallic traces and stacked before dicing into separate die stacks. The traces of each layer of the stacks are interconnected via electroless plating.
1. A method for producing a microelectronic stack comprising:
providing a plurality of wafers having a first face and a second face forming a body thereof for production of microelectronic components, the plurality of wafers each having at least one dielectric region thereon wherein the at least one dielectric region extends from the first face to the second face;
disposing a plurality of conductive metallic traces over the dielectric region in a manner selected from a group consisting of printing, direct imaging, and stenciling wherein each of the conductive metallic traces has at least one corresponding trace on each of the plurality of wafers;
bonding each of the plurality of wafers thereby forming a layered stack of wafers,
wherein the first face of one of the plurality of wafers is bonded to the second face of another one of the plurality of wafers;
dicing the layered stack of wafers along predetermined dicing lanes such that the dicing exposes a vertical edge of a stack wherein the exposed vertical edge is formed of the dielectric region and the plurality of conductive metallic traces; and
interconnecting the metallic traces along the vertical edge through electroless plating such that the metallic traces are electronically interconnected through each layer of the stack.
2. The method of claim 1 wherein the dielectric region for each of the plurality of wafers is consistent in size and shape.
3. The method of claim 1 wherein the dielectric region for each of the plurality of wafers is a different size and dimension.
4. The method of claim 1 wherein the metal used in the electroless plating is selected from a group consisting of nickel, copper, silver, and gold.
5. The method of claim 1 wherein an additional element is bonded to an outer surface of the layered stack of wafers.
6. The method of claim 1 , wherein the distance between the conductive traces on each of the plurality of wafers in the layered stack of wafers is greater than the thickness of one of the plurality of wafers.
7. The method of claim 1 further comprising partially removing some dielectric material from the dielectric region in an area proximal to the at least one of the plurality of conductive traces.
8. The method of claim 1 , wherein bonding comprises providing a bonding layer on at least one of the plurality of wafers and bonding that wafer to another of the plurality of wafers through the bonding layer.
9. The method of claim 1 , wherein at least one of the plurality of metallic traces is a partial trace.
10. The method of claim 9 , wherein the partial trace corresponds to another partial trace on a corresponding bonded wafer.
11. The method of claim 9 , wherein the partial trace corresponds to a regular trace path, wherein the regular trace path is connected to a conductive pad.
12. The method of claim 10 , wherein each of the corresponding partial traces correspond to a regular trace path that is connected to a conductive pad.
13. The method of claim 1 , wherein the microelectronic stack is configured in a chip scale package format.