IP Library Granted Patent US 12,211,821
Granted Patent B2
US 12,211,821 · App. 18/221,171 · Granted Jan 28, 2025

Package-on-package assembly with wire bond vias

Inventors: Ellis Chau (San Jose, CA); Reynaldo Co (Santa Cruz, CA); Roseann Alatorre (San Jose, CA); Philip Damberg (Cupertino, CA); Wei-Shun Wang (Palo Alto, CA); Se Young Yang (Cupertino, CA)
Assignee: Adeia Semiconductor Technologies LLC
H01L24/85H01L21/4853H01L21/56H01L23/3128H01L23/3677H01L23/4334H01L23/49517H01L23/49811H01L23/49816H01L24/06H01L24/43H01L24/78H01L25/105H01L25/50H01L21/565H01L23/3114H01L24/16H01L24/45H01L24/48H01L24/49H01L24/73H01L25/0655H01L25/0657H01L2224/0401H01L2224/05599H01L2224/131H01L2224/16145H01L2224/16225H01L2224/16227H01L2224/32145H01L2224/32225H01L2224/32245H01L2224/45015H01L2224/45124H01L2224/45144H01L2224/45147H01L2224/4554H01L2224/45565H01L2224/48091H01L2224/48145H01L2224/48227H01L2224/4824H01L2224/48245H01L2224/48247H01L2224/48997H01L2224/49171H01L2224/73204H01L2224/73207H01L2224/73253H01L2224/73257H01L2224/73265H01L2224/78301H01L2224/851H01L2224/8518H01L2224/85399H01L2224/85951H01L2224/85986H01L2225/06506H01L2225/0651H01L2225/06513H01L2225/06517H01L2225/06558H01L2225/06562H01L2225/06565H01L2225/06568H01L2225/1023H01L2225/1029H01L2225/1052H01L2225/1058H01L2225/1088H01L2225/1094H01L2924/00011H01L2924/00012H01L2924/00014H01L2924/01013H01L2924/01028H01L2924/01029H01L2924/01047H01L2924/01049H01L2924/12042H01L2924/1431H01L2924/1434H01L2924/15311H01L2924/15331H01L2924/1715H01L2924/181H01L2924/1815H01L2924/19107H01L2924/3511H05K3/3436H05K2201/10515H05K2201/1053Y10T29/49149Y10T29/49151
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Quick Facts
Patent No.
US 12,211,821
App. No.
18/221,171
Granted
Jan 28, 2025
Kind
B2
Abstract

A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer.

Claims (71)

1. A microelectronic package comprising:

a substrate having a first surface;

at least one microelectronic element overlying the first surface;

electrically conductive elements formed within a region of the substrate;

wire bonds having bases bonded to the electrically conductive elements, wherein:

a first end of a first wire bond extends away from a first base of the first wire bond;

a first end of a second wire bond extends away from a first base of the second wire bond;

the first end of the first wire bond comprises a substantially straight portion;

the first end of the second wire bond comprises a second substantially straight portion;

a first middle portion of the first wire bond comprises a bent portion that is bent relative to the substantially straight portion; and

a first middle portion of the second wire bond comprises a second bent portion that is bent relative to the second substantially straight portion; and

a dielectric encapsulation layer covering portions of the wire bonds such that covered portions of the wire bonds are separated from one another by the dielectric encapsulation layer, wherein:

the dielectric encapsulation layer comprises a second surface opposite the first surface of the substrate; and

a portion of the first end of the first wire bond is at or above the second surface of the dielectric encapsulation layer.

2. The microelectronic package of claim 1 , wherein the second bent portion of the second wire bond is curved in substantially the same direction as the bent portion of the first wire bond.

3. The microelectronic package of claim 1 , wherein:

the bent portion of the first wire bond is located a first distance from the first surface;

the second bent portion of the second wire bond is located a second distance from the first surface; and

the first distance is substantially the same as the second distance.

4. The microelectronic package of claim 3 , wherein the second bent portion of the second wire bond is curved in substantially the same direction as the bent portion of the first wire bond.

5. The microelectronic package of claim 1 , wherein the substantially straight portion of the first wire is substantially perpendicular to the first surface.

6. The microelectronic package of claim 5 , wherein the substantially straight portion of the second wire is substantially perpendicular to the first surface.

7. The microelectronic package of claim 1 , wherein:

the bent portion of the first wire bond is located a first distance from the first base of the first wire bond;

the second bent portion of the second wire bond is located a second distance from the first base of the second wire bond; and

the first distance is substantially the same as the second distance.

8. The microelectronic package of claim 1 , wherein the substantially straight portion of the first wire is substantially perpendicular to the substrate.

9. The microelectronic package of claim 8 , wherein the substantially straight portion of the second wire is substantially perpendicular to the substrate.

10. A microelectronic package comprising:

a substrate;

at least one microelectronic element overlying the substrate;

electrically conductive elements formed within a region of the substrate;

wire bonds having bases bonded to the electrically conductive elements, wherein:

a first end of a first wire bond extends away from a first base of the first wire bond;

a first end of a second wire bond extends away from a first base of the second wire bond;

the first end of the first wire bond comprises a substantially straight portion and a surface;

the surface of the first end of the first wire bond comprises a cross-section of the first wire bond;

the first end of the second wire bond comprises a second substantially straight portion;

a first middle portion of the first wire bond comprises a bent portion that is bent relative to the substantially straight portion; and

a first middle portion of the second wire bond comprises a second bent portion that is bent relative to the second substantially straight portion; and

a dielectric encapsulation layer covering portions of the wire bonds such that covered portions of the wire bonds are separated from one another by the dielectric encapsulation layer, wherein the dielectric encapsulation layer does not cover the surface of the first end of the first wire bond.

11. The microelectronic package of claim 10 , wherein the second bent portion of the second wire bond is curved in substantially the same direction as the bent portion of the first wire bond.

12. A microelectronic package comprising:

a substrate having a first surface;

at least one microelectronic element overlying the first surface;

electrically conductive elements at the first surface of the substrate;

wire bonds having bases bonded to the electrically conductive elements, wherein:

a first end of a first wire bond extends away from the electrically conductive elements, the first end of the first wire bond having an end surface comprising a cross-section of the first wire bond;

a first end of a second wire bond extends away from the electrically conductive elements;

the first wire bond comprises a substantially straight portion;

the second wire bond comprises a second substantially straight portion;

a first middle portion of the first wire bond comprises a bent portion that is bent relative to the substantially straight portion to a first direction; and

a first middle portion of the second wire bond comprises a second bent portion that is bent relative to the second substantially straight portion to a second direction;

the first direction is different than the second direction; and

a dielectric encapsulation layer covering portions of the wire bonds such that covered portions of the wire bonds are separated from one another by the dielectric encapsulation layer, wherein the dielectric encapsulation layer does not cover the end surface of the first wire bond.

13. The microelectronic package of claim 12 , wherein the difference between the first direction and the second direction is approximately 90 degrees.

14. The microelectronic package of claim 12 , wherein the difference between the first direction and the second direction is approximately 180 degrees.

15. A microelectronic package comprising:

a substrate having a first surface;

at least one microelectronic element overlying the first surface;

one or more electrically conductive elements at the first surface of the substrate;

wire bonds having bases bonded to the one or more electrically conductive elements, the wire bonds comprising:

a first plurality of wire bonds having first ends extending away from the first surface, the bases of the first plurality of wire bonds having a first pitch, each of the first ends of the first plurality of wire bonds having an end surface comprising a cross-section of a wire bond in the first plurality of wire bonds;

a second plurality of wire bonds having first ends extending away from the first surface, the bases of the second plurality of wire bonds having a second pitch and being disposed in a straight line with the bases of the first plurality of wire bonds, wherein a spacing between the first plurality of wire bonds and the second plurality of wire bonds is larger than either the first pitch or the second pitch; and

a dielectric encapsulation layer covering portions of the wire bonds such that covered portions of the wire bonds are separated from one another by the dielectric encapsulation layer, wherein the dielectric encapsulation layer does not cover the end surfaces of the first plurality of wire bonds.

16. The microelectronic package of claim 15 , wherein the first pitch is substantially the same as the second pitch.

17. The microelectronic package of claim 15 , wherein at least two bases of the bases of the first plurality of wire bonds are bonded to a first electrically conductive element of the one or more electrically conductive elements.

18. The microelectronic package of claim 15 , wherein at least two bases of the bases of the second plurality of wire bonds are bonded to a first electrically conductive element of the one or more electrically conductive elements.

19. The microelectronic package of claim 15 , wherein:

each of the first ends of the second plurality of wire bonds have an end surface comprising a cross-section of a wire bond in the second plurality of wire bonds; and

the dielectric encapsulation layer does not cover the end surfaces of the second plurality of wire bonds.

Assignments (3)
CHANGE OF NAME Recorded Oct 2, 2024
From: INVENSAS LLC
To: ADEIA SEMICONDUCTOR TECHNOLOGIES LLC
Reel/Frame 069087/0330 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 13, 2023
From: CHAU, ELLIS; CO, REYNALDO; ALATORRE, ROSEANN; DAMBERG, PHILIP; WANG, WEI-SHUN; YANG, SE YOUNG
To: INVENSAS CORPORATION
Reel/Frame 064242/0676 →
CHANGE OF NAME Recorded Jul 13, 2023
From: INVENSAS CORPORATION
To: INVENSAS LLC
Reel/Frame 064271/0853 →
Continuity (8)
Continuation 17512123 · Oct 27, 2021
Continuation 16999601 · Aug 21, 2020
Continuation 15699288 · Sep 8, 2017
Continuation 14718719 · May 21, 2015
Division 13795811 · Mar 12, 2013
Continuation 13404408 · Feb 24, 2012
Provisional Application 61547930 · Oct 17, 2011
Related Publication 20240055393A1 · Feb 15, 2024
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Cited By (1)
US 12,653,030