IP Library Granted Patent US 9,276,336
Granted Patent B2
US 9,276,336 · App. 13/410,914 · Granted Mar 1, 2016

Metalized pad to electrical contact interface

Inventor: James Rathburn (Mound, MN)
Assignee: HSIO TECHNOLOGIES, LLC
H01R12/57H01R12/52H01R12/716H05K3/4046H05K7/1069H01R12/523H05K1/141H05K3/3436H05K3/4007H05K2201/049Y10T29/49124
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Quick Facts
Patent No.
US 9,276,336
App. No.
13/410,914
Granted
Mar 1, 2016
Kind
B2
Abstract

A surface mount electrical interconnect to provide an interface between a PCB and contacts on an integrated circuit device. The electrical interconnect includes a substrate with a plurality of recesses arranged along a first surface to correspond to the contacts on the integrated circuit device. Contact members are located in a plurality of the recess. The contact members include contact tips adapted to electrically couple with the contacts on the integrated circuit device. An electrical interface including at least one circuit trace electrically couples the contact member to metalized pads located along a second surface of the substrate at a location offset from a corresponding contact member. A solder ball is attached to a plurality of the metalized pads.

Claims (30)

1. A surface mount electrical interconnect to provide an interface between a PCB and contacts on an integrated circuit device, the electrical interconnect comprising:

an interconnect assembly comprising a plurality of layers bonded together with a plurality of recesses extending through the plurality of bonded layers, the plurality of recesses being arranged on a first surface of the plurality of layers to correspond to the contacts on the integrated circuit device;

contact members located in a plurality of the recesses, the contact members comprising contact tips configured to electrically couple with the contacts on the integrated circuit device;

at least one circuit trace formed on a second surface of the plurality of layers electrically coupling the contact members to metalized pads located on the second surface of the plurality of layers at a location offset from a corresponding contact members;

solder balls attached to a plurality of the metalized pads; and

elongated springs located and arranged along in the plurality of the recesses of the bonded layers configured to bias the contact tips away from the first surface of a to layer.

2. The electrical interconnect of claim 1 wherein at least one of the layers of the interconnect assembly is printed.

3. The electrical interconnect of claim 2 comprising metalized layers formed between layers in the substrate that electrically shield the contact members.

4. The electrical interconnect of claim 1 wherein the circuit traces are located between layers of the substrate.

5. The electrical interconnect of claim 1 comprising metalized layers formed on surfaces of the recesses that electrically couple with the contact members.

6. The electrical interconnect of claim 1 comprising at least one dielectric layer printed on the interface.

7. The electrical interconnect of claim 1 wherein the substrate comprises at least one additional circuitry plane selected from one of a ground plane, a power plane, an electrical connection to other circuit members, a dielectric layer, or a flexible circuit.

8. An electrical interconnect assembly comprising: a housing that retains the electrical interconnect of claim 1 ; an integrated circuit device located in the openings in the housing and electrically coupled to contact tips of the contact members; and a PCB soldered to the solder balls located along the second surface of the substrate to mechanically and electrically couple the integrated circuit to the PCB.

9. A method of making a surface mount electrical interconnect to provide an interface between a PCB and contacts on an integrated circuit device, the method comprising the steps of:

forming an interconnect assembly comprising a plurality of layers bonded together and a plurality of recesses extending through the plurality of layers, the plurality of recesses being arranged along a first surface of the plurality of layers to correspond to the contacts on the integrated circuit device;

locating contact members in a plurality of the recess so that contact tips on the contact members are positioned to electrically couple with the contacts on the integrated circuit device;

forming at least one circuit trace on a second surface of the plurality of layers that electrically couples the contact members to metalized pads located on the second surface of the plurality of layers at a location offset from a corresponding contact members;

attaching solder balls to a plurality of the metalized pads; and

locating elongated springs arranged along in the plurality of the recesses of the bonded layers to bias the contact tips away from the first surface of a top layer.

10. The method of claim 9 comprising printing at least one of the layers of the interconnect assembly.

11. The method of claim 10 comprising forming metalized layers between surfaces in the substrate that electrically shield the contact members.

12. The method of claim 9 comprising locating the circuit traces between layers of the substrate.

13. The method of claim 9 comprising forming metalized layers on surfaces of the recesses that electrically couple with the contact members.

14. The method claim 9 comprising printing at least one dielectric layer on the electrical interface.

15. The method of claim 9 comprising forming at least one additional circuitry plane in the layers of the substrate, the circuit plane comprising one of a ground plane, a power plane, an electrical connection to other circuit members, a dielectric layer, or a flexible circuit.

16. A method of making an electrical interconnect assembly comprising the steps of: locating the electrical interconnect of claim 9 in a housing; locating an integrated circuit device in an openings in the housing; electrically coupling contact tips of the contact members with the contacts on the integrated circuit device; and reflowing the solder balls located along the second surface of the substrate to electrically and mechanically couple the electrical interconnect assembly to a PCB.

17. The electrical interconnect of claim 1 the contact members comprise second ends that extend above the second surface of the plurality of layers.

18. The method of claim 9 comprising locating second ends of the contact members above the second surface of the plurality of layers.

19. The electrical interconnect of claim 1 wherein the plurality of layers are configured to capture the contact members in the recesses.

20. The method of claim 9 comprising configuring the plurality of layers to capture the contact members in the recesses.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 30, 2023
From: HSIO TECHNOLOGIES, LLC
To: LCP MEDICAL TECHNOLOGIES, LLC
Reel/Frame 065391/0193 →
CORRECTIVE ASSIGNMENT TO CORRECT THE SERIAL NUMBER AND FILING DATE ON THE FACE OF THE ASSIGNMENT PREVIOUSLY RECORDED ON REEL 027810 FRAME 0634. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT FROM JAMES RATHBURN TO HSIO TECHNOLOGIES, LLC. Recorded Mar 13, 2012
From: RATHBURN, JAMES
To: HSIO TECHNOLOGIES, LLC
Reel/Frame 027854/0796 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 6, 2012
From: RATHBURN, JAMES
To: HSIO TECHNOLOGIES, LLC
Reel/Frame 027810/0634 →
Continuity (12)
Continuation In Part 13266486
Continuation In Part 13319158
Continuation In Part 13319203
Continuation In Part PCTUS2011033726 · Apr 25, 2011
Continuation In Part PCTUS2011038845 · Jun 2, 2011
Provisional Application 61448288 · Mar 2, 2011
Provisional Application 61181937 · May 28, 2009
Provisional Application 61187873 · Jun 17, 2009
Provisional Application 61221356 · Jun 29, 2009
Provisional Application 61327795 · Apr 26, 2010
Provisional Application 61351114 · Jun 3, 2010
Related Publication 20120164888A1 · Jun 28, 2012