Semiconductor memory device for improving repair efficiency
View Patent ↗A semiconductor memory device includes a transmission line configured to transmit a fuse enable signal for performance of a repair operation; a first repair enable signal generation unit configured to receive the fuse enable signal through the transmission line and generate a first repair enable signal for performing a repair operation for a first bank; and a second repair enable signal generation unit configured to receive the fuse enable signal through the transmission line and generate a second repair enable signal for performing a repair operation for a second bank.
1. A semiconductor memory device comprising:
a transmission line configured to transmit a fuse enable signal for performance of a repair operation;
a first control signal generating section configured to generate a first control signal depending upon a cutting state of a first fuse;
a first output section configured to output a first repair enable signal which is enabled when both the first control signal and the fuse enable signal are enabled;
a second control signal generating section configured to generate a second control signal depending upon a cutting state of a second fuse; and
a second output section configured to output a second repair enable signal which is enabled when both the second control signal and the fuse enable signal are enabled, wherein the first fuse is cut in response to a failure occurring in a memory cell included in the first bank, and the second fuse is cut in response to a failure occurring in a memory cell included in the second bank.
2. The semiconductor memory device according to claim 1 , further comprising:
a fuse enable signal generation unit configured to generate the fuse enable signal which is enabled when a failure occurs in a memory cell included in the first bank or the second bank.
3. The semiconductor memory device according to claim 2 , wherein a fuse cutting operation for a fuse of the fuse enable signal generation unit is performed after packaging is completed.
4. The semiconductor memory device according to claim 3 , wherein the fuse is cut when a failure does not occur in a memory cell included in the first bank or the second bank.
5. The semiconductor memory device according to claim 1 , wherein a fuse cutting operation for the first fuse is performed after packaging is completed.
6. The semiconductor memory device according to claim 5 , wherein the first fuse is cut when a failure does not occur in a memory cell included in the first bank.
7. The semiconductor memory device according to claim 1 , wherein a fuse cutting operation for the second fuse is performed after packaging is completed.
8. The semiconductor memory device according to claim 7 , wherein the second fuse is cut when a failure does not occur in a memory cell included in the second bank.
9. The semiconductor memory device according to claim 1 , further comprising:
a first repair circuit configured to perform the repair operation for the first bank when the first repair enable signal is enabled; and
a second repair circuit configured to perform the repair operation for the second bank when the second repair enable signal is enabled.
10. A semiconductor memory device including first and second banks, comprising:
a fuse enable signal generation unit arranged at a center portion of the semiconductor memory device and configured to generate a fuse enable signal which is enabled when a failure occurs in a memory cell included in the first bank or the second bank;
a first control signal generating section configured to generate a first control signal depending upon a cutting state of a first fuse;
a first output section configured to output a first repair enable signal which is enabled when both the first control signal and the fuse enable signal are enabled;
a second control signal generating section configured to generate a second control signal depending upon a cutting state of a second fuse; and
a second output section configured to output a second repair enable signal which is enabled when both the second control signal and the fuse enable signal are enabled, wherein the first fuse is cut in response to a failure occurring in a memory cell included in the first bank, and the second fuse is cut in response to a failure occurring in a memory cell included in the second bank.
11. The semiconductor memory device according to claim 10 , wherein a fuse cutting operation for a fuse of the fuse enable signal generation unit is performed after packaging is completed.
12. The semiconductor memory device according to claim 11 , wherein the fuse is cut when a failure does not occur in a memory cell included in the first bank or the second bank.
13. The semiconductor memory device according to claim 10 , wherein a fuse cutting operation for the first fuse is performed after packaging is completed.
14. The semiconductor memory device according to claim 13 , wherein the first fuse is cut when a failure does not occur in a memory cell included in the first bank.
15. The semiconductor memory device according to claim 10 , wherein a fuse cutting operation the second fuse is performed after packaging is completed.
16. The semiconductor memory device according to claim 15 , wherein the second fuse is cut when a failure does not occur in a memory cell included in the second bank.
17. The semiconductor memory device according to claim 10 , further comprising:
a first repair circuit configured to perform the repair operation for the first bank when the first repair enable signal is enabled; and
a second repair circuit configured to perform the repair operation for the second bank when the second repair enable signal is enabled.