Method for implementing security of non-volatile memory
View Patent ↗An integrated circuit includes a non-volatile memory module that can censor access to various memory regions based upon a censorship criteria. Information used to implement the censorship criteria is stored at a non-volatile memory location. A one-time programmable non-volatile memory location stores a value representing permanent censorship key. If the permanent censorship key is in an erased state, one or more resources are allowed to modify the non-volatile memory location and disable censorship. If the permanent censorship key has one or more programmed bits, no resource is allowed to modify the non-volatile memory location and disable censorship.
1. A method comprising:
erasing a first memory block, wherein the first memory block includes a first non-volatile memory storage location and a second non-volatile memory storage location;
asserting a first indicator at the first non-volatile memory storage location of an integrated circuit to place a memory of the integrated circuit in a censorship mode of operation, wherein, as a result of being in the censorship mode, access requests from a debug module of the integrated circuit to access the memory need to be authenticated, while access requests from an instruction-based processor to access the memory of the integrated circuit do not need to be authenticated, wherein the erasing the first memory block occurs prior to the asserting the first indicator; and
asserting a second indicator at a first one-time programmable (OTP) non-volatile memory location to place the memory in a permanent censorship mode of operation, wherein as a result of being in the permanent censorship mode instructions executed at the instruction-based processor are prevented from erasing the first storage location, wherein asserting the second indicator occurs after asserting the first indicator, wherein the second indicator comprises a plurality of bits, and asserting the second indicator comprises programming at least a predetermined number of the plurality of bits irrespective of a value of the second indicator; and
authenticating a first access request of the access requests from the debug module based on a secure access key stored at the second non-volatile memory storage location of the integrated circuit, wherein as a result of being in the permanent censorship mode the instructions executed at the instruction-based processor are prevented from erasing the second storage location.
2. The method of claim 1 , wherein the predetermined number is one.
3. The method of claim 1 wherein the memory comprises a plurality of non-volatile memory blocks that are programmable and erasable.
4. The method of claim 3 , wherein as a result of being in permanent censorship mode, the instructions executed at the instruction-based processor are prevented from erasing any of a plurality of storage locations of the first memory block.
5. The method of claim 3 , wherein a second memory block of the plurality of non-volatile memory blocks can be erased and programmed by instructions executed by the instruction-based processor when the memory is in permanent censorship mode.
6. The method of claim 3 , wherein access requests from the debug module of the integrated circuit to access the memory need to be authenticated based upon a third indicator that is stored at the first memory block.
7. The method of claim 3 , wherein the plurality of programmable and erasable non-volatile memory blocks and the OTP non-volatile memory block are located in the same bit cell array.
8. The method of claim 1 , wherein as the result of being in permanent censorship mode the instruction-based processor are prevented from programming the first storage location.
9. The method of claim 8 , wherein the first one-time programmable (OTP) memory location is one of a plurality of OTP memory locations, and wherein the plurality of OTP memory locations can be programmed when the memory is in permanent censorship mode of operation.
10. The method of claim 1 , wherein the memory includes the first storage location.
11. The method of claim 1 , further comprising preventing erase accesses of a plurality of OTP memory locations that include the first OTP location.
12. A device comprising:
a debug module;
an instruction-based processor;
a first memory region that includes a first storage location to store a first indicator and a second storage location to store a secure access key;
a second storage location to store a second indicator, the second storage location being a one-time programmable storage location;
a memory controller coupled to the first memory region, to the second storage location, to the debug module, and to the instruction-based processor,
a censorship control module of the memory controller to require, in response to the first indicator being asserted, authentication of memory access requests to the first memory region by the debug module, and to not require, in response to the first indicator being asserted, the authentication of memory access requests to the first memory region by the instruction-based processor, wherein the authentication of a first access request of the memory access requests to the first memory region by the debug module is based on a secure access key stored at the second storage location, and
an erase module of the of the memory controller to cause, prior to the first indicator being asserted, erasure of the first storage location, and to prevent, in response to the second indicator being asserted, the first storage location from being erased, wherein the second storage location comprises a plurality of bits, and the erase module is to determine the second indicator is asserted in response to a predetermined number of the plurality of bits being programmed, irrespective of a value of the second indicator, wherein as a result of the second indicator being asserted the instruction-based processor is prevented from erasing the any storage location of the first memory region.
13. The device of claim 12 , wherein the first memory region comprises a non-volatile memory region that includes the first storage location, the non-volatile memory region being programmable and erasable.
14. The device of claim 13 , wherein the non-volatile memory region includes a plurality of memory blocks including a first memory block and a second memory block, the first memory block comprising the first storage location; and, in response to the second indicator being set, the erase module to prevent any storage location of the first memory block from being erased, and, in response to the second indicator being asserted, not preventing any storage location of the second memory block from being erased.
15. The method of claim 1 wherein the authenticating the first access request of the access requests from the debug module based on the secure access key is performed during an initial boot routine of the integrated circuit.
16. The method of claim 1 wherein the authenticating the first access request of the access requests from the debug module based on the secure access key is performed based on a password provided with each individual access request.
17. The device of claim 12 wherein the authentication of the first access request of the memory access requests to the first memory region by the debug module are based on the secure access key is performed during a boot routine of the device.