Semiconductor package and lead frame therefor
View Patent ↗A semiconductor package is assembled using first and second lead frames. The first lead frame includes a die flag and the second lead frame includes lead fingers. When the first and second lead frames are mated, the lead fingers surround the die flag. Side surfaces of the die flag are partially etched to form an extended die attach surface on the die flag, and portions of the top surface of each of the lead fingers also are partially etched to form lead finger surfaces that are complementary with the etched side surfaces of the die flag. A semiconductor die is attached to the extended die attach surface and bond pads of the semiconductor die are electrically connected to the lead fingers. An encapsulating material covers the die, electrical connections, and top surfaces of the die flag and lead fingers.
1. A packaged semiconductor device, comprising:
a die flag including a horizontally extended die attach portion;
a plurality of lead fingers that surround and are spaced from the die flag, wherein proximal ends of the lead fingers are located beneath the horizontally extended die attach portion of the die flag, and wherein a top surface of each of the lead fingers is stepped such that a thickness of a distal end of each of the lead fingers is greater than a thickness of the proximal end of each of the lead fingers;
a semiconductor die attached to a top surface of the horizontally extended die attach portion of the die flag and electrically coupled to the lead fingers; and
an encapsulating material that covers the die, the lead fingers and fills gaps between the die flag and at least upper surfaces of the proximal ends of the lead fingers.
2. The packaged semiconductor device of claim 1 , wherein a thickness of the die flag is greater than a thickness of the proximal ends of the lead fingers.
3. The packaged semiconductor device of claim 1 , wherein the encapsulating material comprises epoxy.
4. The packaged semiconductor device of claim 1 , wherein bonding pads of the semiconductor die are electrically coupled to corresponding ones of the lead fingers with bond wires.
5. The packaged semiconductor device of claim 1 , wherein the packaged semiconductor device comprises a quad flat no-lead (QFN) package.
6. A lead frame structure for packaging a semiconductor integrated circuit, the lead frame structure comprising:
a first lead frame including a die flag, wherein the die flag comprises a horizontally extended die attach portion; and
a second lead frame including a plurality of lead fingers, wherein when the first and second lead frames are mated, the lead fingers of the second lead frame surround yet are spaced from the die flag of the first lead frame and a proximal end of each of the lead fingers is located beneath the horizontally extended die attach portion of the die flag, wherein bottom surfaces of the lead fingers and the die flag are coplanar and wherein a top surface of each of the lead fingers is stepped such that a thickness of a distal end of each of the lead fingers is greater than a thickness of the proximal end of each of the lead fingers.
7. The lead frame structure of claim 6 , wherein a thickness of the die flag is greater than the thickness of the distal end of each of the lead fingers.
8. The lead frame structure of claim 6 , wherein a thickness of the proximal end of each of the lead fingers is about 2.5 mils and a vertical distance from a bottom surface of the horizontally extended die attach portion to a bottom surface of the die flag is about 4 mils.
9. The lead frame structure of claim 6 , wherein the first lead frame includes a plurality of die flags and the second lead frame includes a corresponding plurality of sets of leads fingers.