Capacitor and method for fabricating the same

1. A method for fabricating a capacitor, the method comprising:

forming a dielectric layer over a lower electrode on a substrate;

forming an upper electrode over the dielectric layer;

forming a hard mask over the upper electrode;

etching the hard mask to form a hard mask pattern;

etching the upper electrode to make the dielectric layer remain on the lower electrode in a predetermined thickness;

forming an isolation layer along an upper surface of the remaining dielectric layer and the hard mask pattern;

leaving a portion of the isolation layer having a shape of a spacer on one sidewall of the hard mask pattern, the upper electrode, and the dielectric layer; and

etching the lower electrode to be isolated.

2. The method of claim 1 , wherein the leaving of the portion of the isolation layer comprises forming a predetermined portion of the dielectric layer to extend to a lower side of the isolation layer.

3. The method of claim 2 , wherein the forming of the predetermined portion comprises aligning the extended portion of the dielectric layer with one side of the isolation layer.

4. The method of claim 2 , wherein the extended portion of the dielectric layer has a uniform thickness within variation ranging from approximately 10 Å to approximately 20 Å in a wafer.

5. The method of claim 2 , wherein a thickness of the extended portion of the dielectric layer is less than a thickness of a portion of the dielectric layer between the upper electrode and the lower electrode.

6. The method of claim 2 , wherein the extended portion of the dielectric layer has a thickness ranging from approximately 30 Å to approximately 100 Å.

7. The method of claim 1 , wherein the etching of the hard mask is performed by using a photoresist pattern as an etch mask.

8. The method of claim 7 , further comprising:

removing the photoresist pattern after the forming of the hard mask.

9. The method of claim 8 , further comprising:

performing a clean process after the removing of the photoresist pattern.

10. The method of claim 1 , wherein the etching of the upper electrode is performed by a main etch process and an over-etch process, the main etch process having a duration that is greater by a predetermined amount than a duration of the over-etch process.

11. The method of claim 10 , wherein the main etch process is performed for approximately 100 seconds to approximately 130 seconds.

12. The method of claim 10 , wherein the over-etch process is performed for approximately 20 seconds to approximately 30 seconds.

13. The method of claim 10 , wherein the main etch process is performed by using chlorine (Cl) gas and nitrogen (N 2 ) gas.

14. The method of claim 10 , wherein the over-etch process is performed by using boron trichloride (BCl 3 ) gas and argon (Ar) gas.

15. The method of claim 10 , wherein the main etch process is performed until the dielectric layer remains on the lower electrode in a predetermined thickness.

16. The method of claim 1 , wherein the hard mask pattern is formed of an oxide layer or a nitride layer.

17. The method of claim 1 , wherein the isolation layer is formed of an oxide layer or a nitride layer.

18. The method of claim 1 , wherein during the leaving of the isolation layer, an etch-back process or a blanket process is performed.

19. The method of claim 1 , further comprising:

forming an inter-layer insulation layer to cover the upper electrode and the substrate after the etching the lower electrode to be isolated;

etching the inter-layer insulation layer and the hard mask pattern to form first and second holes to partially expose the lower electrode and the upper electrode;

forming first and second vias to fill the first and second holes; and

forming a plurality of upper metal lines, each coupled to the first and second vias.

20. The method of claim 1 , wherein each of the upper and lower electrodes is selected from the group consisting of ruthenium (Ru), strontium ruthenate (SrRuO 3 ), platinum (Pt), tantalum nitride (TaN), tungsten nitride (WN), titanium nitride (TiN), titanium aluminum nitride (TiAlN), cobalt (Co), copper (Cu), hafnium (Hf), and a combination thereof.

21. The method of claim 1 , wherein the dielectric layer is selected from the group consisting of silicon nitride (SiN), silicon oxide (SiO 2 ), aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO), tantalum oxide (Ta 2 O 5 ), strontium titanate (SrTiO 3 ), Perofskite (CaTiO 3 ), lanthanum aluminate (LaAlO 3 ), barium zirconia (BaZrO 3 ), barium zircon titanate (BaZrTiO 3 ), strontium zircon titanate (SrZrTiO 3 ), and a combination thereof.

22. The method of claim 1 , wherein the leaving of the isolation layer comprises separating the isolation layer from the lower electrode using the dielectric layer.

23. The method of claim 1 , wherein, in the etching of the hard mask:

a fluorocarbon gas is used as a main gas; and

a gas selected from the group consisting of oxygen (O 2 ) gas, nitrogen (N 2 ) gas, and argon (Ar) gas is used as a supplementary gas.

24. The method of claim 23 , wherein the fluorocarbon gas is selected from the group consisting of Perfluoromethane (CF 4 ), Trifluoromethane (CHF 3 ), Hexafluoroethane (C 2 F 6 ), Octafluoroethane (C 2 F 8 ), Octafluorocyclobutane (C 4 F 8 ), and a combination thereof.

25. The method of claim 1 , wherein, in the etching of the upper electrode:

a chlorine-based gas is used as a main gas; and

a gas selected from the group consisting of nitrogen gas and argon gas is used as a supplementary gas.

26. The method of claim 25 , wherein the chlorine-based gas is selected from the group consisting of chlorine (Cl 2 ), Boron Trichloride (BCl 3 ), carbon chloride (CCl), hydrochloride (HCl), chlorotrifluoromethane (CF 3 Cl), tetraclorosilane (SiCl 4 ), and a combination thereof.