Non-volatile memory array architecture optimized for hi-reliability and commercial markets
View Patent ↗A sense amplifier arrangement includes a first sense amplifier having a first input and a second input. A second sense amplifier has a first input and a second input. A switching circuit is configured to selectively couple the first input of the first sense amplifier to a first bit line in the array and the second input of the first sense amplifier to a first bit line in the array to selectively couple the first input of the first sense amplifier to the first bit line in the array, the first input of the second sense amplifier to the second bit line in the array, and the second inputs of the first and second sense amplifiers to a reference voltage.
1. In a non-volatile memory array arranged as a plurality of rows and columns of non-volatile memory cells, memory cells in each column of the array being selectively coupleable to a bit line associated with that column of the array, a memory cell sensing circuit comprising:
a first sense amplifier arrangement coupleable to the memory array to differentially read a complementary bit stored in a pair of memory cells; and
a second sense amplifier arrangement coupleable to the memory array to read a single-ended bit stored in a single memory cell;
wherein the first and second sense amplifier arrangements are selectively coupled to the memory array in response to at least one selection signal.
2. The memory cell sensing circuit of claim 1 wherein the first sense amplifier arrangement comprises a first sense amplifier having a first input coupled to a first bit line and a second input coupled to a second bit line in response to a first state of the at least one selection signal.
3. The memory cell sensing circuit of claim 1 wherein the second sense amplifier arrangement comprises:
a first sense amplifier having a first input coupled to a first bit line and a second input coupled to a reference voltage in response to a second state of the at least one selection signal; and
a second sense amplifier having a first input coupled to a second bit line and a second input coupled to the reference voltage in response to the second state of the at least one selection signal.
4. The memory cell sensing circuit of claim 2 wherein the second sense amplifier arrangement comprises:
the first sense amplifier having the first input coupled to the first bit line and the second input coupled to a reference voltage the second state of the at least one selection signal; and
a second sense amplifier having a first input coupled to the second bit line and a second input coupled to the reference voltage in response to the second state of the at least one selection signal.
5. The memory cell sensing circuit of claim 1 wherein:
the first sense amplifier arrangement comprises a first sense amplifier coupleable to the memory array, said first sense amplifier having a first input coupled to a first bit line and a second input coupled to a second bit line, said first sense amplifier arrangement operative to differentially read a complementary bit stored in a pair of memory cells in response to a first state of the at least one selection signal; and
the second sense amplifier arrangement comprises a second sense amplifier having a first input coupled to the first bit line and a second input coupled to the reference voltage, and a third sense amplifier having a first input coupled to the second bit line and a second input coupled to the reference voltage in response to the second state of the at least one selection signal.
6. The memory cell sensing circuit of claim 1 wherein:
the first sense amplifier arrangement comprises a first sense amplifier having a first input coupled to a first bit line and a second input coupled to a second bit line in response to a first state of the at least one selection signal; and
the second sense amplifier arrangement comprises the first sense amplifier having the first input coupled to the first bit line and the second input coupled to a reference voltage for a first period of time, and the first sense amplifier having the first input coupled to the reference voltage and the second input coupled to the second bit line for a second period of time in response to a second state of the at least one selection signal.
7. In a non-volatile memory array arranged as a plurality of rows and columns of non-volatile memory cells, memory cells in each column of the array being selectively coupleable to a bit line associated with that column of the array, a sense amplifier arrangement including:
a sense amplifier having a first input and a second input; and
a switching circuit configured to selectively:
couple the first input of the sense amplifier to a first bit line in the array and the second input of the sense amplifier to a second bit line in the array;
couple the first input of the sense amplifier to the first bit line in the array and the second input of the sense amplifier to a reference voltage; or
couple the second input of the sense amplifier to the second bit line in the array and the first input of the sense amplifier to the reference voltage.
8. In a non-volatile memory array arranged as a plurality of rows and columns of non-volatile memory cells, memory cells in each column of the array being selectively coupleable to a bit line associated with that column of the array, a sense amplifier arrangement including:
a first sense amplifier having a first input and a second input;
a second sense amplifier having a first input and a second input, the second input coupled to a reference voltage; and
a switching circuit configured to selectively:
couple the first input of the first sense amplifier to a first bit line in the array and the second input of the first sense amplifier to a second bit line in the array; or
couple the first input of the first sense amplifier to the first bit line in the array, the first input of the second sense amplifier to the second bit line in the array, and the second input of the first sense amplifier to the reference voltage.
9. In a non-volatile memory array arranged as a plurality of rows and columns of non-volatile memory cells, memory cells in each column of the array being selectively coupleable to a bit line associated with that column of the array, a sense amplifier arrangement including:
a first sense amplifier having a first input and a second input;
a second sense amplifier having a first input and a second input, the second input of the second sense amplifier coupled to a reference voltage;
a third sense amplifier having a first input and a second input, the second input of the third sense amplifier coupled to a reference voltage; and
a switching circuit configured to selectively:
couple the first input of the first sense amplifier to a first bit line in the array and the second input of the first sense amplifier to a second bit line in the array, or
couple the first input of the second sense amplifier to the first bit line in the array, and the first input of the third sense amplifier to the second bit line in the array.
10. A method for operating a non-volatile memory including a pair of memory cells in a row and associated with two adjacent columns in the array, the method comprising:
selecting a first mode of operation;
if the first mode of operation is selected:
programming the pair of memory cells with complementary data as a single bit;
coupling the bit line associated with the first column of the adjacent pair of columns to the first input of a sense amplifier and coupling the bit line associated with the second column of the adjacent pair of columns to the second input of the sense amplifier; and
asserting the word line for the row thus reading the programmed complementary data out to the sense amplifier on the bit lines associated with the adjacent columns;
if the second mode of operation is selected:
programming the pair of memory cells individually with data;
coupling the bit line associated with the first column of the two adjacent columns to the first input of a sense amplifier and coupling a reference voltage to the second input of the sense amplifier;
asserting the word line for the row thus reading the programmed data from the memory cell in the first column out to the sense amplifier;
coupling the reference voltage to the first input of the sense amplifier and coupling the bit line associated with the second column of the two adjacent columns to the second input of a sense amplifier; and
asserting the word line for the row thus reading the programmed data from the memory cell in the second column out to the sense amplifier.
11. A method for operating a non-volatile memory including a pair of memory cells in a row and associated with two adjacent columns in the array, the method comprising:
selecting between a first mode of operation and a second mode of operation;
if the first mode of operation is selected:
programming the pair of memory cells with complementary data as a single bit;
coupling the bit line associated with the first column of the adjacent pair of columns to the first input of a first sense amplifier and coupling the bit line associated with the second column of the adjacent pair of columns to the second input of the first sense amplifier; and
asserting the word line for the row and reading the complementary data read out to the sense amplifier on the bit lines associated with the adjacent columns, if the second mode of operation is selected:
programming the pair of memory cells individually with data;
coupling the bit line associated with the first column of the two adjacent columns to the first input of the first sense amplifier and a reference voltage to the second input of the first sense amplifier;
coupling the bit line associated with the second column of the two adjacent columns to a first input of a second sense amplifier; and
asserting the word line for the row thus reading the data from the memory cell in the first column out to the first sense amplifier and reading the data from the memory cell in the second column out to the second sense amplifier.
12. A method for operating a non-volatile memory including a pair of memory cells in a row and associated with two adjacent columns in the array, the method comprising:
selecting between a first mode of operation and a second mode of operation;
if the first mode of operation is selected:
programming the pair of memory cells with complementary data as a single bit;
coupling the bit line associated with the first column of the adjacent pair of columns to the first input of a first sense amplifier and coupling the bit line associated with the second column of the adjacent pair of columns to the second input of the first sense amplifier; and
asserting the word line for the row thus reading the programmed complementary data out to the sense amplifier on the bit lines associated with the adjacent columns, if the second mode of operation is selected:
programming the pair of memory cells individually with data;
coupling the bit line associated with the first column of the two adjacent columns to the first input of a second sense amplifier and a reference voltage to the second input of the second sense amplifier;
coupling the bit line associated with the second column of the two adjacent columns to a first input of a third sense amplifier and a reference voltage to the second input of the third sense amplifier; and
asserting the word line for the row thus reading the data from the memory cell in the first column out to the second sense amplifier and reading the data from the memory cell in the second column out to the third sense amplifier.