Granted Patent B2

US 9,026,887 · App. 13/421,088 · Granted May 5, 2015

Inventors: Troy A. Manning (Meridian, ID); Troy D. Larsen (Meridian, ID); Martin L. Culley (Boise, ID)

Assignee: Micron Technology, Inc.

G06F11/108G06F8/44

Abstract

Claims (116)

1. A method for operating a memory, the method comprising:

error coding a number of logical pages of data into a number of codewords; and

writing the number of codewords to a number of physical pages of memory,

wherein the number of logical pages of data is different than the number of physical pages of memory, and

wherein the number of codewords is different than the number of logical pages of data and the number of physical pages of memory.

2. The method of claim 1 , wherein error coding the number of logical pages of data into the number of codewords comprises error coding a non-integer number of logical pages of data as an integer number of codewords.

3. The method of claim 1 wherein writing the number of codewords to the number of physical pages of memory comprises writing the integer number of codewords to an integer number of physical pages of memory.

4. The method of claim 1 , wherein error coding the number of logical pages of data further comprises:

error coding physical page metadata and a first portion of a first logical page of data into a first codeword; and

error coding a second portion of the first logical page of data into a second codeword; and

wherein writing the number of codewords further comprises writing the first codeword and the second codeword to a first physical page of memory.

5. The method of claim 4 , wherein error coding the number of logical pages of data further comprises:

error coding a third portion of the first logical page of data and a first portion of a second logical page of data into a third codeword; and

error coding a second portion of the second logical page of data into a fourth codeword; and

wherein writing the number of codewords further comprises writing the third codeword and the fourth codeword to the first physical page of memory.

6. The method of claim 5 , wherein error coding the number of logical pages of data further comprises:

error coding the physical page metadata, a third portion of the second logical page of data, and a first portion of a third logical page of data into a fifth codeword; and

writing the fifth codeword to a second physical page of memory.

7. The method of claim 1 , wherein error coding comprises using a controller of a memory apparatus to error code the number of logical pages of data into the number of codewords.

8. A method for operating a memory, the method comprising:

error coding data using a variable codeword wrapper size and a variable codeword payload size of a fixed total codeword size; and

receiving an input indicating a particular codeword wrapper size prior to error coding the data based on a desired amount of error correction for the codeword payload.

9. The method of claim 7 , wherein the method further comprises:

setting a particular codeword payload size based on the particular codeword wrapper size; and

error coding the data into codewords having the particular codeword payload size.

10. The method of claim 7 , wherein the method further comprises:

communicating with a host based on logical page size; and

buffer managing the memory based on the total codeword size.

11. The method of claim 10 , wherein buffer managing the memory based on total codeword size comprises buffering a payload of a respective codeword in each of a plurality of logical buffer segments; and

wherein communicating with the host based on logical page size comprises communicating a logical page of data to the host, the logical page of data comprising a respective codeword payload from each of the plurality of logical buffer segments.

12. The method of claim 8 , wherein error coding comprises using a controller of a memory apparatus to error code data using the variable codeword wrapper size and the variable codeword payload size of the total codeword size.

13. A method for operating memory, the method comprising:

reading a stripe of data from a plurality of physical pages of memory, wherein each of the plurality of physical pages of memory stores a respective plurality of codewords; and

combining payload portions of more than one of the respective plurality of codewords from one of the plurality of physical pages of memory to form a logical page of data.

14. The method of claim 13 , wherein the method further comprises combining payload portions of more than one of the respective plurality of codewords from more than one of the plurality of physical pages of memory to form an additional logical page of data.

15. The method of claim 13 , wherein the method further comprises combining payload portions of the respective plurality of codewords from the plurality of physical pages of memory to form a plurality of logical pages of data.

16. The method of claim 13 , wherein combining the payload portions comprises combining an entire payload portion of a first one of the respective plurality of codewords with less than an entirety of a payload portion of a second one of the respective plurality of codewords to form the logical page of data.

17. The method of claim 13 , wherein reading the stripe of data comprises reading an integer number of codewords.

18. The method of claim 13 , wherein combining payload portions comprises using a controller of a memory apparatus to combine payload portions of more than one of the respective plurality of codewords from one of the plurality of physical pages of memory to form the logical page of data.

19. A method for operating memory, the method comprising:

encoding only a portion of a logical page of data including a starting portion of the logical page of data into a particular codeword; and

writing a plurality of physical pages of memory as a stripe, wherein one of the plurality of physical pages of memory includes an integer number of codewords including the particular codeword.

20. The method of claim 19 , wherein the method further comprises mapping a location of the starting portion of the logical page of data to the stripe.

21. The method of claim 20 , wherein the method further comprises reading the logical page of data by:

using the mapping to identify the stripe that includes the starting portion of the logical page of data; and

calculating an offset into the stripe to identify the one of the plurality of physical pages of memory and the particular codeword that includes the starting portion of the logical page of data.

22. The method of claim 19 , wherein the method further comprises determining an address for the logical page of data based on a set of parameters including:

physical page of memory total size;

physical page metadata size;

codeword total size;

codeword payload size;

host sector size; and

logical page metadata size.

23. The method of claim 19 , wherein encoding comprises using a controller of a memory apparatus to encode only the portion of the logical page of data including the starting portion of the logical page of data into the particular codeword.

24. A method for operating a memory, the method comprising:

error coding a non-integer number of logical pages of data into an integer number of codewords; and

writing the integer number of codewords to a number of physical pages of memory, wherein the non-integer number of logical pages of data is different than the number of physical pages of memory.

25. The method of claim 24 , wherein writing the integer number of codewords to the number of physical pages of memory comprises writing the integer number of codewords to an integer number of physical pages of memory.

26. An apparatus, comprising:

a number of memory devices; and

a controller coupled to the number of memory devices and configured to:

error code a number of logical pages of data into a number of codewords; and

write the number of codewords to a number of physical pages of memory,

wherein the number of logical pages of data is different than the number of physical pages of memory, and

wherein the number of codewords is different than the number of logical pages of data and the number of physical pages of memory.

27. The apparatus of claim 26 , wherein the controller being configured to error code the number of logical pages of data into the number of codewords further comprises the controller being configured to error code a non-integer number of logical pages of data as an integer number of codewords.

28. The apparatus of claim 26 , wherein the controller being configured to write the number of codewords to the number of physical pages of memory further comprises the controller being configured to write the integer number of codewords to an integer number of physical pages of memory.

29. The apparatus of claim 26 , wherein the controller being configured to error code the number of logical pages of data further comprises the controller being configured to:

error code physical page metadata and a first portion of a first logical page of data into a first codeword; and

error code a second portion of the first logical page of data into a second codeword; and

wherein the controller being configured to write the number of codewords further comprises the controller being configured to write the first codeword and the second codeword to a first physical page of memory.

30. The apparatus of claim 29 , wherein the controller being configured to error code the number of logical pages of data further comprises the controller being configured to:

error code a third portion of the first logical page of data and a first portion of a second logical page of data into a third codeword; and

error code a second portion of the second logical page of data into a fourth codeword; and

wherein the controller being configured to write the number of codewords further comprises the controller being configured to write the third codeword and the fourth codeword to the first physical page of memory.

31. The apparatus of claim 30 , wherein the controller being configured to error code the number of logical pages of data further comprises the controller being configured to:

error code the physical page metadata, a third portion of the second logical page of data, and a first portion of a third logical page of data into a fifth codeword; and

write the fifth codeword to a second physical page of memory.

32. An apparatus, comprising:

a number of memory devices; and

a controller coupled to the number of memory devices and configured to:

error code data using a variable codeword wrapper size and a variable codeword payload size of a fixed total codeword size; and

receive an input indicating a particular codeword wrapper size prior to error coding the data based on a desired amount of error correction for the codeword payload.

33. The apparatus of claim 32 , wherein the controller is further configured to:

receive an input setting a particular codeword payload size based on the particular codeword wrapper size; and

error code the data into codewords having the particular codeword payload size.

34. The apparatus of claim 32 , wherein the controller is further configured to:

communicate with a host based on logical page size; and

buffer manage the memory based on the total codeword size.

35. The apparatus of claim 34 , wherein the controller being configured to buffer manage the memory based on total codeword size further comprises the controller being configured to buffer a payload of a respective codeword in each of a plurality of logical buffer segments; and

wherein the controller being configured to communicate with the host based on logical page size further comprises the controller being configured to communicate a logical page of data to the host, the logical page of data comprising a respective codeword payload from each of the plurality of logical buffer segments.

36. An apparatus, comprising:

a number of memory devices; and

a controller coupled to the number of memory devices and configured to:

read a stripe of data from a plurality of physical pages of memory, wherein each of the plurality of physical pages of memory stores a respective plurality of codewords; and

combine payload portions of more than one of the respective plurality of codewords from one of the plurality of physical pages of memory to form a logical page of data.

37. The apparatus of claim 36 , wherein the controller is further configured to combine payload portions of more than one of the respective plurality of codewords from more than one of the plurality of physical pages of memory to form an additional logical page of data.

38. The apparatus of claim 36 , wherein the controller is further configured to combine payload portions of the respective plurality of codewords from the plurality of physical pages of memory to form a plurality of logical pages of data.

39. The apparatus of claim 36 , wherein the controller being configured to combine the payload portions further comprises the controller being configured to combine an entire payload portion of a first one of the respective plurality of codewords with less than an entirety of a payload portion of a second one of the respective plurality of codewords to form the logical page of data.

40. The apparatus of claim 36 , wherein the controller being configured to read the stripe of data further comprises the controller being configured to read an integer number of codewords.

41. An apparatus, comprising:

a number of memory devices; and

a controller coupled to the number of memory devices and configured to:

encode only a portion of a logical page of data including a starting portion of the logical page of data into a particular codeword; and

write a plurality of physical pages of memory as a stripe, wherein one of the plurality of physical pages of memory includes an integer number of codewords including the particular codeword.

42. The apparatus of claim 41 , wherein the controller is further configured to map a location of the starting portion of the logical page of data to the stripe.

43. The apparatus of claim 42 , wherein the controller is further configured to read the logical page of data by:

using the mapping to identify the stripe that includes the starting portion of the logical page of data; and

calculating an offset into the stripe to identify the one of the plurality of physical pages of memory and the particular codeword that includes the starting portion of the logical page of data.

44. The apparatus of claim 41 , wherein the controller is further configured to determine an address for the logical page of data based on a set of parameters including:

physical page of memory total size;

physical page metadata size;

codeword total size;

codeword payload size;

host sector size; and

logical page metadata size.

Assignments (8)

Continuity (1)