Semiconductor device and method of manufacturing the same
View Patent ↗According to one embodiment, a method of manufacturing a MOS semiconductor device. In the method, a gate electrode is formed on a gate insulating film provided on a channel region which is a part of an Si layer and which is interposed between a source/drain region, and a film mainly includes of Ge is made to grow on the source/drain region. Then, and the film mainly includes of Ge is made to react with a metal, forming an intermetallic compound film having a depthwise junction position identical to a growth interface of the film mainly includes of Ge.
1. A method of manufacturing a MOS semiconductor device, comprising:
forming a gate electrode on a gate insulating film provided on a channel region which is a part of an Si layer and which is interposed between a source/drain region;
growing a film comprising Ge, on the source/drain region;
making the film comprising Ge react with a metal, thereby forming an intermetallic compound film having a depthwise junction position identical to a growth interface of the film comprising Ge, and
injecting ions into the intermetallic compound film to form the source/drain region, and injecting ions of an element capable of modulating the height of a Schottky barrier into the intermetallic compound film.
2. The method of claim 1 , wherein the film comprising Ge is selectively formed on the source/drain region after the gate electrode has been formed.
3. The method of claim 1 , wherein the film comprising Ge is formed on the source/drain region before the gate electrode is formed.
4. The method of claim 1 , wherein Ni is used as a metal to react with the film comprising Ge, and germanidation of Ge and Ni is performed at a temperature ranging from 275 to 325° C.
5. The method of claim 1 , wherein the Si layer has plane orientation (100) or (110).
6. The method of claim 1 , wherein an SiGe film is used as the film comprising Ge.
7. A method of manufacturing a 3D-structured MOS semiconductor device, comprising:
forming a gate electrode on a gate insulating film provided on a channel region which is a fin-shaped part of an Si layer formed on a substrate and which is interposed between a source/drain region;
growing a film comprising Ge, on the source/drain region;
making the film comprising Ge react with a metal, thereby forming an intermetallic compound film having a depthwise junction position identical to a growth interface of the film comprising Ge, and
injecting ions into the intermetal compound film to form the source/drain region in, and injection ions of an element capable of modulating the height of a Schottky barrier into the intermetallic compound film.
8. The method of claim 7 , wherein the film comprising Ge is selectively formed on the source/drain region after the gate electrode has been formed.
9. The method of claim 7 , wherein the film comprising Ge is formed on the source/drain region before the gate electrode is formed.
10. The method of claim 7 , wherein Ni is used as a metal to react with the film comprising Ge, and germanidation of Ge and Ni is performed at a temperature ranging from 275 to 325° C.
11. The method of claim 7 , wherein the Si layer has plane orientation (100) or (110).
12. The method of claim 7 , wherein an SiGe film is used as the film comprising Ge.