Sample and hold circuit and differential sample and hold circuit
View Patent ↗A sample and hold circuit is provided. The circuit includes a first switch configured to receive an input, a second switch coupled to a second end of the first switch, a first capacitor coupled to the second end of the first switch, a third switch coupled to a second end of the first capacitor, a fourth switch coupled between the second end of the first capacitor and ground, an op-amp having a first input coupled to the second end of the third switch and a second input connected to ground and an output coupled to the second end of the second switch, a fifth switch coupled to a second end of the third switch, a second capacitor coupled between the output of the op-amp and a second end of the fifth switch, and a sixth switch coupled between the second end of the second capacitor and ground.
1. A sample and hold circuit configured to operate in a first phase and a second phase, comprising:
a first capacitor;
a second capacitor;
an operational amplifier having an input and an output; and
a plurality of switches selectively coupling the first capacitor, the second capacitor and the operational amplifier,
wherein the plurality of switches are configured to receive a plurality of control signals such that in the first phase the first capacitor is configured to be coupled between an input of the sample and hold circuit and ground and the second capacitor is configured to be coupled between the input of the operational amplifier and the output of the operational amplifier, and in the second phase the first capacitor is configured to be coupled between the input of the operational amplifier and the output of the operational amplifier and the second capacitor is configured to be coupled between the output of the operational amplifier and ground,
wherein a first switch of the plurality of switches is directly coupled between the first capacitor and the input of the sample and hold circuit, a second switch of the plurality of switches is directly coupled between the first capacitor and the output of the operational amplifier, a third switch of the plurality of switches is directly coupled between the first capacitor and the input of the operational amplifier, a fourth switch of the plurality of switches is directly coupled between the first capacitor and ground, a fifth switch of the plurality of switches is directly coupled between the input of the operational amplifier and the second capacitor, and a sixth switch of the plurality of switches is directly coupled between the second capacitor and ground.
2. The sample and hold circuit of claim 1 , wherein the first switch, the fourth switch and the fifth switch are configured to receive a first control signal.
3. The sample and hold circuit of claim 2 , wherein the second switch, the third switch and the sixth switch are configured to receive a second control signal, wherein the second control signal is an inverse of the first control signal.
4. The sample and hold circuit of claim 1 , wherein in the first phase an output of the sample and hold circuit is substantially equal to the output of the sample and hold circuit in a prior second phase, and in the second phase the output of the sample and hold circuit is substantially equal to an input to the sample and hold circuit during the first phase delayed by one-half clock cycle.
5. The sample and hold circuit of claim 1 , wherein in the first phase the first capacitor is electrically isolated from the operational amplifier and the second capacitor.
6. The sample and hold circuit of claim 1 , further comprising:
a third capacitor; and
a fourth capacitor,
wherein the plurality of switches are configured to selectively couple the third capacitor, the fourth capacitor and the operational amplifier and to receive the plurality of control signals such that in the first phase the third capacitor is configured to be coupled between a second input of the sample and hold circuit and ground and the fourth capacitor is configured to be coupled between a second input of the operational amplifier and a second output of the operational amplifier, and in the second phase the third capacitor is configured to be coupled between the second input of the operational amplifier and the second output of the operational amplifier and the fourth capacitor is configured to be coupled between the second output of the operational amplifier and ground.
7. The sample and hold circuit of claim 6 , wherein a seventh switch of the plurality of switches is coupled between the third capacitor and a second input of the sample and hold circuit, a eighth switch of the plurality of switches is coupled between the third capacitor and a second output of the operational amplifier, a ninth switch of the plurality of switches is coupled between the third capacitor and a second input of the operational amplifier, a tenth switch of the plurality of switches is coupled between the third capacitor and ground, an eleventh switch of the plurality of switches is coupled between the second input of the operational amplifier and the fourth capacitor, and a twelfth switch of the plurality of switches is coupled between the fourth capacitor and ground.
8. The sample and hold circuit of claim 7 , wherein the seventh switch, the tenth switch and the eleventh switch are configured to receive a first control signal and the eighth switch, the ninth switch and the twelfth switch are configured to receive a second control signal, wherein the second control signal is an inverse of the first control signal.
9. The sample and hold circuit of claim 8 , wherein in the first phase the third capacitor is electrically isolated from the operational amplifier and the fourth capacitor.
10. The sample and hold circuit of claim 9 , wherein the operational amplifier is not reset between the first phase and the second phase.
11. The sample and hold circuit of claim 6 , wherein the sample and hold circuit is configured to sample an automotive radar signal.
12. A sample and hold circuit, comprising:
a first switch having a first end and a second end, wherein the first end of the first switch is configured to receive a first input voltage;
a second switch having a first end and a second end, wherein the first end of the second switch is directly coupled to the second end of the first switch;
a first capacitor having a first end and a second end, wherein the first end of the first capacitor is directly coupled to the second end of the first switch;
a third switch having a first end and a second end, wherein the first end of the third switch is directly coupled to the second end of the first capacitor;
a fourth switch having a first end and a second end, wherein the first end of the fourth switch is directly coupled to the second end of the first capacitor and the second end of the fourth switch is coupled to a ground;
an operational amplifier having a first input, a second input and a first output, wherein the first input is directly coupled to the second end of the third switch and the first output is directly coupled to the second end of the second switch;
a fifth switch having a first end and a second end, wherein the first end of the fifth switch is directly coupled to the second end of the third switch;
a second capacitor having a first end and a second end, wherein the first end of the second capacitor is directly coupled to the first output of the operational amplifier and the second end of the second capacitor is directly coupled to the second end of the fifth switch; and
a sixth switch having a first end and a second end, wherein the first end of the sixth switch is directly coupled to the second end of the second capacitor and the second end of the sixth switch is coupled to the ground.
13. The sample and hold circuit of claim 12 , wherein the second input of the operational amplifier is coupled to ground.
14. The sample and hold circuit of claim 13 , wherein the first switch, third switch, and fifth switch are configured to receive a first control signal and the second switch, fourth switch, and sixth switch are configured to receive a second control signal.
15. The sample and hold circuit of claim 14 , wherein in a first phase the first switch, third switch and fifth switch are closed and the second switch, fourth switch and sixth switch are open and in a second phase the first switch, third switch and fifth switch are open and the second switch, fourth switch and sixth switch are closed.
16. The sample and hold circuit of claim 15 , further comprising:
a seventh switch having a first end and a second end, wherein the first end of the seventh switch is configured to receive a second input voltage;
a eighth switch having a first end and a second end, wherein the first end of the eighth switch is coupled to the second end of the seventh switch;
a third capacitor having a first end and a second end, wherein the first end of the third capacitor is coupled to the second end of the seventh switch;
a ninth switch having a first end and a second end, wherein the first end of the ninth switch is coupled to the second end of the third capacitor;
a tenth switch having a first end and a second end, wherein the first end of the tenth switch is coupled to the second end of the third capacitor and the second end of the tenth switch is coupled to ground;
an eleventh switch having a first end and a second end, wherein the first end of the eleventh switch is coupled to the second end of the ninth switch;
a fourth capacitor having a first end and a second end, wherein the first end of the fourth capacitor is coupled to a second output of the operational amplifier and the second end of the fourth capacitor is coupled to the second end of the eleventh switch;
a twelfth switch having a first end and a second end, wherein the first end of the twelfth switch is coupled to the second end of the fourth capacitor and the second end of the twelfth switch is coupled to ground,
wherein the second input of the operational amplifier is coupled to the second end of the ninth switch and the second output is connected to the second end of the eighth switch.
17. The sample and hold circuit of claim 16 , wherein the seventh switch, ninth switch, and eleventh switch are configured to receive the first control signal and the eighth switch, tenth switch, and twelfth switch are configured to receive the second control signal.
18. The sample and hold circuit of claim 17 , wherein in the first phase the seventh switch, ninth switch, and eleventh switch are closed and the eighth switch, tenth switch, and twelfth switch are open and in the second phase the seventh switch, ninth switch, and eleventh switch are open and the eighth switch, tenth switch, and twelfth switch are closed.
19. The sample and hold circuit of claim 15 , wherein the operational amplifier is not reset between the first phase and the second phase.