IP Library Granted Patent US 8,611,148
Granted Patent B2
US 8,611,148 · App. 13/428,305 · Granted Dec 17, 2013

Data state-dependent channel boosting to reduce channel-to-floating gate coupling in memory

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,611,148
App. No.
13/428,305
Granted
Dec 17, 2013
Kind
B2
Abstract

In a programming operation, selected storage elements on a selected word line are programmed while unselected storage elements on the selected word line are inhibited from programming by channel boosting. To provide a sufficient but not excessive level of boosting, the amount of boosting can be set based on a data state of the unselected storage element. A greater amount of boosting can be provided for a lower data state which represents a lower threshold voltage and hence is more vulnerable to program disturb. A common boosting scheme can be used for groups of multiple data states. The amount of boosting can be set by adjusting the timing and magnitude of voltages used for a channel pre-charge operation and for pass voltages which are applied to word lines. In one approach, stepped pass voltages on unselected word lines can be used to adjust boosting for channels with selected data states.

Claims (28)

1. A method for operating a non-volatile storage system, comprising:

performing one portion of a programming operation for programming storage elements in a group of non-volatile storage elements formed on a substrate to a plurality of different programmed states, in which a first storage element reaches an associated target programmed data state, a second storage element remains in an erased state, and a third storage element is programmed toward, but does not reach, an associated target programmed data state; and

performing a subsequent portion of the programming operation which includes performing a programming iteration in which, before applying a program pulse to the group of non-volatile storage elements: the first storage element is locked out from further programming, a first channel region of the substrate which is associated with the first storage element is boosted to a first level, and a second channel region of the substrate which is associated with the second storage element is boosted to a second level, higher than the first level.

2. The method of claim 1 , wherein:

the program pulse is applied to the group of non-volatile storage elements via a selected word line.

3. The method of claim 1 , wherein:

the first channel region is boosted to the first level using a first boosting scheme which is associated with a group of one or more data states which does not include the erased state; and

the second channel region is boosted to the second level using a second boosting scheme which is associated with the erased state but not the group of one or more data states.

4. The method of claim 3 , further comprising, in connection with the performing the programming iteration:

reading a latch associated with the first storage element to determine that the first storage element has reached a data state which is in the group of one or more data states; and

reading a latch associated with the second storage element to determine that the second storage element is in the erased state but not the group of one or more data states.

5. The method of claim 1 , further comprising:

in the one portion of the programming operation, a fourth storage element reaches an associated target programmed data state which is higher than the associated target programmed data state of the first storage element; and

in the programming iteration, before the applying the program pulse to the group of non-volatile storage elements: the fourth storage element is locked out from further programming, and a channel region of the substrate which is associated with the fourth storage element is boosted to a level which is lower than the first level.

6. A non-volatile storage system, comprising:

a group of non-volatile storage elements formed on a substrate, the group of non-volatile storage elements comprises a first, second and third non-volatile storage elements, and the substrate a comprises a first channel region which is associated with the first storage element and a second channel region which is associated with the second storage element; and

a control circuit, the control circuit: performs one portion of a programming operation for programming storage elements in the group of non-volatile storage elements to a plurality of different programmed states, in which the first storage element reaches an associated target programmed data state, the second storage element remains in an erased state, and the third storage element is programmed toward, but does not reach, an associated target programmed data state, and, to perform a subsequent portion of the programming operation, performs a programming iteration in which, before a program pulse is applied to the group of non-volatile storage elements: the first storage element is locked out from further programming, the first channel region of the substrate is boosted to a first level, and the second channel region of the substrate is boosted to a second level, higher than the first level.

7. The non-volatile storage system of claim 6 , wherein:

the program pulse is applied to the group of non-volatile storage elements via a selected word line.

8. The non-volatile storage system of claim 6 , wherein:

the first channel region is boosted to the first level using a first boosting scheme which is associated with a group of one or more data states which does not include the erased state; and

the second channel region is boosted to the second level using a second boosting scheme which is associated with the erased state but not the group of one or more data states.

9. The non-volatile storage system of claim 8 , wherein, in connection with the programming iteration:

the control circuit reads a latch associated with the first storage element to determine that the first storage element has reached a data state which is in the group of one or more data states; and

reads a latch associated with the second storage element to determine that the second storage element is in the erased state but not the group of one or more data states.

10. The non-volatile storage system of claim 6 , wherein:

in the one portion of the programming operation, a fourth storage element reaches an associated target programmed data state which is higher than the associated target programmed data state of the first storage element; and

in the programming iteration, before the applying the program pulse to the group of non-volatile storage elements: the fourth storage element is locked out from further programming, and a channel region of the substrate which is associated with the fourth storage element is boosted to a level which is lower than the first level.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 8, 2025
From: SANDISK TECHNOLOGIES, INC.
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 070778/0175 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 31, 2024
From: SANDISK TECHNOLOGIES LLC
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 069796/0423 →
CHANGE OF NAME Recorded May 25, 2016
From: SANDISK TECHNOLOGIES INC
To: SANDISK TECHNOLOGIES LLC
Reel/Frame 038807/0898 →