IP Library Granted Patent US 9,446,305
Granted Patent B2
US 9,446,305 · App. 13/430,269 · Granted Sep 20, 2016

System and method for improving the graphics performance of hosted applications

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Quick Facts
Patent No.
US 9,446,305
App. No.
13/430,269
Granted
Sep 20, 2016
Kind
B2
Abstract

A system and method for efficiently processing a video stream using limited hardware and/or software resources. For example, one embodiment of a computer-implemented method for efficiently processing a video stream with a processor pipeline having a plurality of pipeline stages, comprises: identifying a bottleneck stage within the processor pipeline the bottleneck stage processing frames of the video stream; receiving a feedback signal from the bottleneck stage at one or more upstream stages, the feedback signal providing an indication of the speed at which the bottleneck stage is processing the frames of the video stream; and responsively adjusting the speed at which the one or more upstream stages are processing frames of the video stream to approximate the speed at which the bottleneck stage is processing the frames of the video stream.

Claims (14)

1. A computer implemented method for efficiently processing a video stream with a processor pipeline having a plurality of pipeline stages, comprising:

identifying a bottleneck stage within the processor pipeline, the bottleneck stage having a first clock and processing frames of the video stream;

receiving a feedback signal from the bottleneck stage at one or more upstream stages, at least one of the upstream stages having a second clock, the feedback signal including information as to time required by the bottleneck stage to operate on data and information as to time the data spent queued; and

responsively adjusting the speed at which the one or more upstream stages are processing frames of the video stream to approximate the speed at which the bottleneck stage is processing the frames of the video stream, wherein the speed is adjusted, at least in part, by modifying a frequency of the second clock.

2. The method as in claim 1 wherein the processor pipeline includes one or more stages within a central processor unit (CPU) and one or more stages within a graphics processing unit (GPU).

3. The method as in claim 1 wherein the video stream is generated by program code of a video game being played by a user.

4. The method as in claim 3 wherein the video game is executed on a hosting server, wherein the user plays the video game from a client computer, and wherein the pipeline stages are stages within the hosting server.

5. A method, comprising operations of:

identifying a bottleneck stage within a processor pipeline with a plurality of pipeline stages, wherein the bottleneck stage has a first clock and processes frames of a video stream;

receiving a feedback signal from the bottleneck stage at one or more upstream stages, wherein at least one of the upstream stages has a second clock and wherein the feedback signal includes information as to time required by the bottleneck stage to operate on data and information as to time the data spent queued; and

responsively adjusting the speed at which the one or more upstream stages are processing frames of the video stream to approximate the speed at which the bottleneck stage is processing the frames of the video stream, wherein the speed is adjusted, at least in part, by modifying a frequency of the second clock, and wherein each of the operations is performed by hardware components that contain hardwired logic.

6. The method as in claim 1 , wherein the processor pipeline includes one or more stages within a central processor unit (CPU) and one or more stages within a graphics processing unit (GPU).

7. The method as in claim 1 , wherein the video stream is generated by program code of a video game being played by a user.

8. The method as in claim 7 , wherein the video game is executed on a hosting server, wherein the user plays the video game from a client computer, and wherein the pipeline stages are stages within the hosting server.

Assignments (7)
MERGER Recorded Mar 30, 2020
From: SONY INTERACTIVE ENTERTAINMENT AMERICA LLC
To: SONY INTERACTIVE ENTERTAINMENT LLC
Reel/Frame 053323/0567 →
CHANGE OF NAME Recorded May 5, 2016
From: SONY COMPUTER ENTERTAINMENT AMERICA LLC
To: SONY INTERACTIVE ENTERTAINMENT AMERICA LLC
Reel/Frame 038626/0637 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 1, 2015
From: OL2, INC.
To: SONY COMPUTER ENTERTAINMENT AMERICA LLC
Reel/Frame 035354/0237 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ZIP CODE OF RECEIVING PARTY PREVIOUSLY RECORDED ON REEL 031002 FRAME 0348. ASSIGNOR(S) HEREBY CONFIRMS THE ZIP CODE OF RECEIVING PARTY SHOULD BE CHANGED FROM 94303 TO 94043. Recorded Sep 18, 2013
From: INSOLVENCY SERVICES GROUP, INC.
To: OL2, INC.
Reel/Frame 031244/0935 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 13, 2013
From: INSOLVENCY SERVICES GROUP, INC.
To: OL2, INC.
Reel/Frame 031002/0348 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 13, 2013
From: ONLIVE, INC.
To: INSOLVENCY SERVICES GROUP, INC.
Reel/Frame 031001/0964 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 9, 2012
From: DIETRICH, DOUGLAS SIM, JR.; BENITEZ, NICO; COTTER, TIMOTHY
To: ONLIVE, INC.
Reel/Frame 028756/0225 →