Concurrent memory bank access and refresh request queuing
View Patent ↗An apparatus and system associated with memory are disclosed herein. In various embodiments, an apparatus may include first circuitry configured to queue pending refresh requests for a plurality of memory banks; and second circuitry coupled to the first circuitry and configured to set a refresh flag in response to a determination that a number of queued pending refresh requests for a memory bank from the plurality of memory banks exceeds a predetermined number. Other embodiments may be disclosed and/or claimed.
1. An apparatus, comprising:
first circuitry configured to queue pending refresh requests for a plurality of memory banks;
second circuitry coupled to the first circuitry and configured to set a refresh flag in response to a determination that a number of queued pending refresh requests for a memory bank from the plurality of memory banks exceeds a predetermined number; and
third circuitry coupled to the first and second circuitries, wherein the third circuitry is configured to determine the number of queued pending refresh requests based on a difference between a count from a wrap around refresh request counter and a count from a wrap around refresh address counter.
2. The apparatus of claim 1 , further comprising the wrap around refresh request counter coupled with the first circuitry.
3. The apparatus of claim 1 , further comprising the wrap around refresh address counter coupled with the first circuitry.
4. The apparatus of claim 1 , wherein the second circuitry is further configured to output the refresh flag to an external device.
5. The apparatus of claim 1 , further comprising the plurality of memory banks coupled with the first circuitry.
6. A method, comprising:
queuing pending refresh requests for a plurality of memory banks;
determining whether a number of queued pending refresh requests for a first memory bank from the plurality of memory banks exceeds a predetermined number; and
setting a refresh flag in response to a determination that the number of queued pending refresh requests for the first memory bank exceeds the predetermined number;
wherein said determining comprises determining the number of queued pending refresh requests based on a difference between a count from a wrap around refresh request counter and a count from a wrap around refresh address counter.
7. The method of claim 6 , further comprising incrementing the count of the wrap around refresh request counter in response to a refresh request.
8. The method of claim 6 , further comprising storing, in the wrap around refresh address counter, a row address of the first memory bank to be refreshed.
9. The method of claim 6 , further comprising outputting the refresh flag to an external device.
10. A system, comprising:
a memory array having a plurality of memory banks; and
a refresh control circuit coupled to the memory array and configured to:
perform an access operation on a first memory bank from the plurality of memory banks; and
retire, substantially simultaneously with a performance of the access operation, a pending refresh request for a second memory bank from the plurality of memory banks;
wherein the refresh control circuit includes:
first circuitry configured to queue pending refresh requests for the second memory bank;
second circuitry coupled to the first circuitry and configured to set a refresh flag in response to a determination that a number of queued pending refresh requests for the second memory bank exceeds a predetermined number; and
third circuitry coupled to the first and second circuitries, wherein the third circuitry is configured to determine the number of queued pending refresh requests based on a difference between a count from a wrap around refresh request counter and a count from a wrap around refresh address counter.
11. The system of claim 10 , wherein the refresh control circuit further comprises the wrap around refresh request counter coupled with the first circuitry.
12. The system of claim 10 , wherein the refresh control circuit further comprises the wrap around refresh address counter coupled with the first circuitry.
13. The system of claim 10 , wherein the second circuitry is further configured to output the refresh flag to a device external to the refresh control circuit.
14. The system of claim 10 , wherein the refresh control circuit is further configured to retire the pending refresh request during a clock cycle and also perform the access operation during the clock cycle.
15. The system of claim 10 , wherein the refresh control circuit is further configured to retire, substantially simultaneously with the access operation, another pending refresh request for a third memory bank from the plurality of memory banks.
16. The system of claim 10 , wherein the refresh control circuit is further configured to perform, substantially simultaneously with the retirement of the pending refresh request, another access operation on a third memory bank from the plurality of memory banks.
17. The system of claim 10 , wherein the refresh control circuit is further configured to limit a number of simultaneous access and refresh operations on the plurality of memory banks.