Patent Assignment
Reel/Frame 048036/0968
Assignment of Assignor's Interest
Recorded: 2019-01-16
Pages: 14
Assignor
INTELLECTUAL VENTURES ASSETS 97 LLC
Executed: 2018-11-30
Assignee
INNOMEMORY LLC
100 COMMONS RD, SUITE #11, DRIPPING SPRINGS, TEXAS, 78620
Covered Properties
(34)
Bit Line Cross-Over Layout Arrangement
Patent:
6,163,475 →
Application:
09/285,232 →
Hierarchical Dynamic Memory Array Architecture Using Read Amplifiers Separate from Bit Line Sense Amplifiers
Patent:
6,198,682 →
Application:
09/329,975 →
Method of and Apparatus for Sharing Redundancy Circuits Between Memory Arrays Within a Semiconductor Memory Device
Patent:
6,208,569 →
Application:
09/356,805 →
Dynamic Memory Array Having Write Data Applied to Selected Bit Line Sense Amplifiers Before Sensing to Write Associated Selected Memory Cells
Patent:
6,212,109 →
Application:
09/372,320 →
Flash Memory Architecture and Method of Operation
Patent:
6,288,938 →
Application:
09/433,245 →
Equilibration Circuit and Method Using a Pulsed Equilibrate Signal and a Level Equilibrate Signal
Patent:
6,104,653 →
Application:
09/451,042 →
Programmable and Electrically Configurable Latch Timing Circuit
Patent:
6,462,998 →
Application:
09/474,351 →
Word line straps using two differentlayers of metal
Patent:
6,266,264 →
Application:
09/499,265 →
Integrated circuit random access memory capable of reading either one or more than one data word in a single clock cycle
Patent:
6,240,046 →
Application:
09/502,983 →
Merging write cycles by comparing at least a portion of the respective write cycle addresses
Patent:
6,356,485 →
Application:
09/503,048 →
Intializing memory cells within a dynamic memory array prior to performing internal memory operations
Patent:
6,282,135 →
Application:
09/503,049 →
Memory array having selected word lines driven to an internally-generated boosted voltage that is substantially independent of VDD
Patent:
6,373,753 →
Application:
09/503,050 →
Generating a Tail Current for a Differential Transistor Pair Using a Capacitive Device to Project a Current Flowing Through a Current Source Device Onto a Node Having a Different Voltage Than the Current Source Device
Patent:
6,462,584 →
Application:
09/503,108 →
Dynamic memory array bit line sense amplifier enabled to drive toward, but stopped before substantially reaching, a source of voltage
Patent:
6,208,575 →
Application:
09/503,109 →
Non-volatile memory cell capable of being programmed and erased through substantially separate areas of one of its drain-side and source-side regions
Patent:
6,243,298 →
Application:
09/503,982 →
Priority Encoder with Multiple Match Function for Content Addressable Memories and Methods for Implementing the Same
Patent:
6,392,910 →
Application:
09/642,253 →
Content address memory circuit with redundant array and method for implementing the same
Patent:
6,275,406 →
Application:
09/650,971 →
Content addressable memory having read/write capabilities that do not interrupt continuous search cycles
Patent:
6,339,539 →
Application:
09/651,426 →
Variable Width Content Addressable Memory Device for Searching Variable Width Data
Patent:
6,553,453 →
Application:
09/654,316 →
Three port content addressable memory device and methods for implementing the same
Patent:
6,362,990 →
Application:
09/654,319 →
An Integrated Circuit Having an Eeprom and Flash Eprom
Patent:
6,501,684 →
Application:
09/668,431 →
Method for Reducing the Width of a Global Data Bus in a Memory Architecture
Patent:
6,538,928 →
Application:
09/689,219 →
A Structure and Method of Operating an Array of Non-Volatile Memory Cell with Souce-Side Programming
Patent:
6,416,556 →
Application:
09/757,088 →
Non-Volatile Memory Architecture and Method of Operation
Integrated Circuit Random Access Memory Capable of Automatic Internal Refresh of Memory Array
Patent:
6,871,261 →
Application:
09/999,563 →
Integrated Circuit Having an Eeprom and Flash Eprom
Integrated Circuit Having an Eeprom and Flash Eprom Using a Memory Cell with Source-Side Programming
Integrated Circuit Random Access Memory Capable of Automatic Internal Refresh of Memory Array
Methods and Circuitry for Built-in Self-Testing of Content Addressable Memories
Patent:
41,659 →
Application:
11/208,134 →
Methods and Circuitry for Built-in Self-Testing of Content Addressable Memories
Patent:
41,992 →
Application:
11/514,286 →
Concurrent Memory Bank Access and Refresh Retirement
Concurrent Memory Bank Access and Refresh Request Queuing
Refresh Request Queuing Circuitry
Refresh Request Queuing Circuitry
Related Assignments
(4)
Other recorded transfers of the patents in this record — the chain of ownership.
Merger
Oct 16, 2015
From: CORE NETWORKS LLC
To: XYLON LLC
Reel/Frame 036876/0519 →
Merger
Oct 30, 2015
From: THERA CONSULTANTS LLC
To: XYLON LLC
Reel/Frame 037014/0456 →
Nunc Pro Tunc Assignment
Dec 14, 2018
From: INTELLECTUAL VENTURES I LLC
To: INTELLECTUAL VENTURES ASSETS 97 LLC
Reel/Frame 047782/0207 →
Nunc Pro Tunc Assignment
Dec 14, 2018
From: XYLON LLC
To: INTELLECTUAL VENTURES ASSETS 97 LLC
Reel/Frame 047782/0379 →