Refresh request queuing circuitry
View Patent ↗An apparatus and system associated with memory are disclosed herein. In various embodiments, an apparatus may include first circuitry to determine a number of queued pending refresh requests for a memory bank based on a comparison of a count from a refresh-request counter to a count from a refresh-address counter; and second circuitry to set a refresh flag in response to a determination that the number of queued pending refresh requests exceeds a predetermined number. Other embodiments may be disclosed and/or claimed.
1. An apparatus, comprising:
a refresh-request counter;
a refresh-address counter; and
circuitry coupled to the refresh-request counter and the refresh-address counter, wherein the circuitry is configured to:
determine a refresh request is pending for a memory bank based on a comparison of a count from the refresh-request counter to a count from the refresh-address counter;
determine that the count from the refresh-request counter exceeds the count from the refresh-address counter by a predetermined number; and
set a refresh flag in response to the determination that the count from the refresh-request counter exceeds the count from the refresh address counter by the predetermined number.
2. The apparatus of claim 1 , wherein the refresh-request counter is configured to periodically receive refresh requests from a decoder.
3. The apparatus of claim 1 , further comprising:
an address multiplexor coupled to the refresh-address counter and configured to receive a row address to be refreshed.
4. The apparatus of claim 1 , wherein the second circuitry is configured to output the refresh flag to an external device.
5. The apparatus of claim 1 , wherein the memory bank is coupled to the first circuitry.
6. A method, comprising:
determining a refresh request is pending based on a comparison of a count from a refresh-request counter to a count from a refresh-address counter;
determining that the count from the refresh-request counter exceeds the count from the refresh-address counter by a predetermined number; and
setting a refresh flag in response to the determination that the count from the refresh-request counter exceeds the count from the refresh-address counter by the predetermined number.
7. The method of claim 6 , further comprising:
receiving a refresh request for the memory bank; and
incrementing the count of the refresh-request counter in response to receipt of the refresh request.
8. The method of claim 6 , further comprising:
storing, in the refresh-address counter, a row address of the memory bank to be refreshed.
9. The method of claim 8 , further comprising:
refreshing the row address.
10. The method of claim 9 , further comprising:
refreshing the row address during a clock cycle in response to a determination that an access operation is not scheduled to be performed on the memory bank in the clock cycle.
11. A system, comprising:
a memory array having a plurality of memory banks; and
control circuitry coupled to the memory array, wherein the control circuitry is configured to:
perform an access operation on a first memory bank of the plurality of memory banks; and
retire, substantially simultaneously with a performance of the access operation, a pending refresh request for a second memory bank of the plurality of memory banks;
wherein the control circuitry includes:
first circuitry configured to determine a refresh request is pending for the second memory bank based on a comparison of a count from a refresh-request counter to a count from a refresh-address counter; and
second circuitry configured to set a refresh flag in response to a determination that the count from the refresh-request counter exceeds the count from the refresh-address counter by a predetermined number.
12. The system of claim 11 , wherein the control circuitry further comprises:
a plurality of refresh control circuits respectively coupled to the plurality of memory banks;
wherein a first refresh control circuit of the plurality of refresh control circuits is coupled to the second memory bank and includes the first and second circuitry.
13. The system of claim 11 , wherein the second circuitry is further configured to output the refresh flag to a device external to the control circuitry.
14. The system of claim 11 , wherein the control circuitry is further configured to retire pending refresh requests for the first memory bank during clock cycles in which access operations are not scheduled on the first memory bank.
15. An apparatus comprising:
a refresh-request counter;
a refresh-address counter; and
circuitry coupled to the refresh-request counter and the refresh-address counter, wherein the circuitry is configured to:
compute a difference in counts of the refresh-request counter and the refresh-address counter;
determine a refresh request is pending for a memory bank based on the computed difference in counts of the refresh-request counter and the refresh-address counter; and
set a refresh flag in response to a determination that the count of the refresh-request counter exceeds the count of the refresh-address counter by a predetermined number.
16. The apparatus of claim 15 , wherein the refresh-request counter is configured to periodically receive refresh requests from a decoder.
17. The apparatus of claim 15 , further comprising:
an address multiplexor coupled to the refresh-address counter and configured to receive a row address to be refreshed.
18. The apparatus of claim 15 , wherein the circuitry is configured to output the refresh flag to an external device.
19. The apparatus of claim 15 , wherein the memory bank is coupled to the circuitry.