Patent Assignment
Reel/Frame 047782/0207
Nunc Pro Tunc Assignment
Recorded: 2018-12-14
Pages: 8
Assignor
INTELLECTUAL VENTURES I LLC
Executed: 2018-11-01
Assignee
INTELLECTUAL VENTURES ASSETS 97 LLC
251 LITTLE FALLS DRIVE, WILMINGTON, DELAWARE, 19808
Covered Properties
(26)
Bit Line Cross-Over Layout Arrangement
Patent:
6,163,475 →
Application:
09/285,232 →
Hierarchical Dynamic Memory Array Architecture Using Read Amplifiers Separate from Bit Line Sense Amplifiers
Patent:
6,198,682 →
Application:
09/329,975 →
Dynamic Memory Array Having Write Data Applied to Selected Bit Line Sense Amplifiers Before Sensing to Write Associated Selected Memory Cells
Patent:
6,212,109 →
Application:
09/372,320 →
Flash Memory Architecture and Method of Operation
Patent:
6,288,938 →
Application:
09/433,245 →
Equilibration Circuit and Method Using a Pulsed Equilibrate Signal and a Level Equilibrate Signal
Patent:
6,104,653 →
Application:
09/451,042 →
Programmable and Electrically Configurable Latch Timing Circuit
Patent:
6,462,998 →
Application:
09/474,351 →
Word line straps using two differentlayers of metal
Patent:
6,266,264 →
Application:
09/499,265 →
Integrated circuit random access memory capable of reading either one or more than one data word in a single clock cycle
Patent:
6,240,046 →
Application:
09/502,983 →
Merging write cycles by comparing at least a portion of the respective write cycle addresses
Patent:
6,356,485 →
Application:
09/503,048 →
Intializing memory cells within a dynamic memory array prior to performing internal memory operations
Patent:
6,282,135 →
Application:
09/503,049 →
Memory array having selected word lines driven to an internally-generated boosted voltage that is substantially independent of VDD
Patent:
6,373,753 →
Application:
09/503,050 →
Generating a Tail Current for a Differential Transistor Pair Using a Capacitive Device to Project a Current Flowing Through a Current Source Device Onto a Node Having a Different Voltage Than the Current Source Device
Patent:
6,462,584 →
Application:
09/503,108 →
Dynamic memory array bit line sense amplifier enabled to drive toward, but stopped before substantially reaching, a source of voltage
Patent:
6,208,575 →
Application:
09/503,109 →
Non-volatile memory cell capable of being programmed and erased through substantially separate areas of one of its drain-side and source-side regions
Patent:
6,243,298 →
Application:
09/503,982 →
An Integrated Circuit Having an Eeprom and Flash Eprom
Patent:
6,501,684 →
Application:
09/668,431 →
Method for Reducing the Width of a Global Data Bus in a Memory Architecture
Patent:
6,538,928 →
Application:
09/689,219 →
A Structure and Method of Operating an Array of Non-Volatile Memory Cell with Souce-Side Programming
Patent:
6,416,556 →
Application:
09/757,088 →
Non-Volatile Memory Architecture and Method of Operation
Integrated Circuit Random Access Memory Capable of Automatic Internal Refresh of Memory Array
Patent:
6,871,261 →
Application:
09/999,563 →
Integrated Circuit Having an Eeprom and Flash Eprom
Integrated Circuit Having an Eeprom and Flash Eprom Using a Memory Cell with Source-Side Programming
Integrated Circuit Random Access Memory Capable of Automatic Internal Refresh of Memory Array
Concurrent Memory Bank Access and Refresh Retirement
Concurrent Memory Bank Access and Refresh Request Queuing
Refresh Request Queuing Circuitry
Refresh Request Queuing Circuitry
Related Assignments
(2)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Dec 10, 2009
From: ARLENE H. PROEBSTING AND TODD A. PROEBSTING, TRUSTEES OF THE ROBERT J. PROEBSTING AND ARLENE H. PROEBSTING FAMILY TRUST
To: PRFA TECHNOLOGY FUND, LLC
Reel/Frame 023637/0291 →
Assignment of Assignor's Interest
Jan 16, 2019
From: INTELLECTUAL VENTURES ASSETS 97 LLC
To: INNOMEMORY LLC
Reel/Frame 048036/0968 →