IP Library Granted Patent US 8,283,764
Granted Patent B2
US 8,283,764 · App. 13/436,432 · Granted Oct 9, 2012

Microelectronic assembly with an embedded waveguide adapter and method for forming the same

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Quick Facts
Patent No.
US 8,283,764
App. No.
13/436,432
Granted
Oct 9, 2012
Kind
B2
Abstract

A microelectronic assembly and a method for forming a microelectronic assembly are provided. A semiconductor substrate is provided. The semiconductor substrate has first and second opposing sides and first and second portions. A tuning depression is formed on the second opposing side and the second portion of the semiconductor substrate. A radio frequency conductor is formed on the first opposing side of the first semiconductor substrate. The radio frequency conductor has a first end on the first portion of the first semiconductor substrate and a second end on the second portion of the first semiconductor substrate. A microelectronic die having an integrated circuit formed therein is attached to the first opposing side and the first portion of the semiconductor substrate such that the integrated circuit is electrically connected to the first end of the radio frequency conductor.

Claims (38)

1. A microelectronic assembly, comprising:

a first semiconductor substrate having first and second portions and first and second opposing sides, the first semiconductor comprising a first tuning depression on the second opposing side and the second portion thereof and a radio frequency conductor on the first opposing side thereof, the radio frequency conductor having a first end on the first portion thereof and a second end on the second portion thereof;

a microelectronic die having an integrated circuit formed therein attached to the first opposing side and the first portion of the first semiconductor substrate such that the integrated circuit is electrically connected to the first end of the radio frequency conductor; and

a second semiconductor substrate having first and second portions and first and second opposing sides attached to the first semiconductor substrate such that the first opposing side of the first semiconductor substrate is adjacent to the second opposing side of the second semiconductor substrate, the second semiconductor substrate comprising a second tuning depression on the second opposing side and the second portion thereof and a die depression on the second opposing side and the first portion thereof, wherein the second end of the radio frequency conductor is positioned between the first and second tuning depressions and the microelectronic die is at least partially positioned within the die depression.

2. The microelectronic assembly of claim 1 , wherein the semiconductor substrate comprises silicon, gallium arsenide, gallium nitride, or a combination thereof.

3. The microelectronic assembly of claim 2 , wherein the integrated circuit is a millimeter wave (mmW) device.

4. The microelectronic assembly of claim 3 , further comprising a plurality of conductive vias in the first semiconductor substrate and the second semiconductor substrate, each of the conductive vias extending between the first and second opposing sides of the respective substrate.

5. The microelectronic assembly of claim 4 , wherein at least some of the conductive vias are in the first portion of the first semiconductor substrate and are electrically connected to the integrated circuit when the microelectronic die is attached to the first portion of the first semiconductor substrate.

6. The microelectronic assembly of claim 5 , wherein the first and second semiconductor substrates are semiconductor wafers.

7. A microelectronic assembly, comprising:

first and second semiconductor substrates, each semiconductor substrate having first and second portions and first and second opposing sides;

a first tuning depression on the second opposing side and the second portion of the first semiconductor substrate;

a radio frequency conductor on the first opposing side of the first semiconductor substrate, the radio frequency conductor having a first end on the first portion of the first semiconductor substrate and a second end on the second portion of the first semiconductor substrate;

a microelectronic die having an integrated circuit formed therein attached to the first opposing side and the first portion of the first semiconductor substrate such that the integrated circuit is electrically connected to the first end of the radio frequency conductor;

a second tuning depression on the second opposing side and the second portion of the second semiconductor substrate; and

a die depression on the second opposing side and the first portion of the second semiconductor substrate;

wherein the second semiconductor substrate is attached to the first semiconductor substrate such that the first opposing side of the first semiconductor substrate is adjacent to the second opposing side of the second semiconductor substrate, the microelectronic die is at least partially positioned within the die depression, and the second end of the radio frequency conductor is positioned between the first and second tuning depressions.

8. The microelectronic assembly of claim 7 , wherein the first and second semiconductor substrates comprise a semiconductor material, and wherein the semiconductor material is silicon, gallium arsenide, gallium nitride, or a combination thereof.

9. The microelectronic assembly of claim 8 , wherein the first and second tuning depressions comprise etched features formed in the first and second semiconductor substrates, respectively.

10. The microelectronic assembly of claim 9 , wherein the integrated circuit is a millimeter wave (mmW) device.

11. The microelectronic assembly of claim 10 , further comprising a plurality of conductive vias formed in the first semiconductor substrate and the second semiconductor substrate, each of the conductive vias extending between the first and second opposing sides of the respective substrate.

12. The microelectronic assembly of claim 11 , wherein at least some of the conductive vias are formed in the first portion of the first semiconductor substrate and are electrically connected to the integrated circuit when the microelectronic die is attached to the first portion of the first semiconductor substrate.

13. The microelectronic assembly of claim 11 , wherein the first and second semiconductor substrates are semiconductor wafers.

14. A microelectronic assembly, comprising:

a semiconductor substrate having first and second opposing sides and comprising a plurality of package portions, each of the plurality of package portions having a first and a second portion;

a plurality of tuning depressions formed on the second opposing side of the semiconductor substrate, each of the plurality of tuning depressions being on the second portion of a respective one of the package portions;

a plurality of radio frequency conductors formed on the first opposing side of the semiconductor substrate, each of the plurality of radio frequency conductors having a first end on the first portion of a respective one of the package portions and a second end on the second portion of the respective one of the package portions; and

a microelectronic die having an integrated circuit formed therein attached to the first portion of each of the package portions of the semiconductor substrate such that the integrated circuit is electrically connected to the first end of the radio frequency conductor on the respective package portion.

15. The microelectronic assembly of claim 14 , wherein the semiconductor substrate comprises a semiconductor material, and wherein the semiconductor material is silicon, gallium arsenide, gallium nitride, or a combination thereof.

16. The microelectronic assembly of claim 15 , wherein the semiconductor substrate is a semiconductor wafer.

17. The microelectronic assembly of claim 16 , wherein the integrated circuit in each of the microelectronic dies is a millimeter wave (mmW) device.

18. The microelectronic assembly of claim 17 , further comprising a plurality of conductive vias formed in each of the package portions of the semiconductor substrate, each of the conductive vias extending between the first and second opposing sides of the semiconductor substrate.

19. The microelectronic assembly of claim 18 , wherein at least some of the conductive vias are formed in the first portion of each of package portions of the semiconductor substrate and are electrically connected to the integrated circuit when the respective microelectronic die is attached to the first portion of the package portion.

20. The microelectronic assembly of claim 19 , further comprising:

a second semiconductor substrate having first and second opposing sides and comprising a plurality of second package portions, each of the second package portions having a first portion and a second portion;

a plurality of second tuning depressions formed on the second opposing side of the second semiconductor substrate, each of the plurality second tuning depressions being on the second portion of a respective one of the second package portions; and

a plurality of die depressions formed on the second opposing side of the second semiconductor substrate, each of the plurality die depressions being on the first portion of a respective one of the second package portions;

wherein each of the second package portions of the second semiconductor substrate are attached to a respective one of the package portions of the semiconductor substrate such that the first opposing side of each of the package portions is adjacent to the second opposing side of the respective second package portion, the microelectronic die on each package portion is at least partially positioned within the die depression of the respective second package portion, and the second end of each radio frequency conductor is positioned between the respective first and second tuning depressions.

Assignments (31)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040632 FRAME: 0001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Sep 21, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 044209/0047 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040632/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
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PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
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PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
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SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Apr 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
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SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Apr 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Apr 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 13, 2012
From: TANG, JINBANG
To: FREESCALE SEMICONDUCTOR, INC.
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