Semiconductor device including plural chips stacked to each other
View Patent ↗Disclosed herein is a device that includes a plurality of stacked core chips and an interface chip that controls the core chips. Each of the core chips includes a memory cell array, a penetration electrode, and an output circuit that outputs read data that are read from the memory cell array to the penetration electrode. The penetration electrode respectively provided in the core chips are commonly connected with each other, and the output circuits respectively provided in the core chips are activated in response to a read clock signal supplied from the interface chip.
1. A semiconductor device comprising:
a plurality of core chips stacked to each other, each of the core chips including a memory cell array, a data terminal, and an output circuit that outputs read data that is read out from the memory cell array to the data terminal; and
an interface chip that controls the core chips,
wherein the data terminals of the core chips are commonly connected to each other so as to form a data path common to the core chips, the output circuits are activated in response to a first read clock signal supplied from the interface chip, and the interface chip receives the read data through the data path,
wherein each of the data terminals includes a first penetration electrode that is provided through an associated one of the core chips, and the first penetration electrodes are arranged in the same planar position as viewed from a stacking direction and are short-circuited to each other, and
wherein each of the core chips further includes an input circuit that latches the read data that is read out from the memory cell array, the output circuit outputs the read data latched by the input circuit to the first penetration electrode, and the input circuit latches the read data in response to a second read clock signal generated in the core chip.
2. The semiconductor device as claimed in claim 1 , wherein the interface chip includes a command decoder that generates a third read clock signal based on a read command supplied from outside, and a first delay circuit that generates the first read clock signal by delaying the third read clock signal.
3. The semiconductor device as claimed in claim 2 , wherein each of the core chips further includes a second delay circuit that generates the second read clock signal by delaying the third read clock signal.
4. The semiconductor device as claimed in claim 2 , wherein each of the core chips further includes a second penetration electrode, the second penetration electrodes of the core chips are commonly connected to each other so as to form a first signal path common to the core chips, and the interface chip commonly supplies the first read clock signal to the core chips through the first signal path.
5. The semiconductor device as claimed in claim 4 , wherein each of the core chips further includes a third penetration electrode, the third penetration electrodes of the core chips are commonly connected to each other so as to form a second signal path common to the core chips, the interface chip commonly supplies a chip address to the core chips through the second signal path, and each of the core chips causes the first read clock signal to be valid when the chip address supplied from the interface chip matches a unique chip address allocated to the corresponding core chip.
6. The semiconductor device as claimed in claim 5 , wherein each of the core chips further includes a fourth penetration electrode, the fourth penetration electrodes of the core chips are commonly connected to each other so as to form a third signal path common to the core chips, the interface chip commonly supplies the third read clock signal to the core chips through the third signal path, and each of the core chips causes the third read clock signal to be valid when the chip address supplied from the interface chip matches the unique chip address allocated to the corresponding core chip.
7. The semiconductor device as claimed in claim 1 , wherein each of the core chips includes a plurality of pairs of the output circuit and the input circuit, the read data read out from the memory cell array is commonly supplied to input nodes of the input circuits, each of output nodes of the input circuits is connected to an associated one of input nodes of the output circuits, output nodes of the output circuits are commonly connected to the first penetration electrode, any one of the input circuits is activated based on the second read clock signal, and any one of the output circuits is activated based on the first read clock signal.
8. The semiconductor device as claimed in claim 1 , wherein the interface chip further includes a FIFO circuit that latches the read data sequentially supplied through the data path and sequentially outputs the read data latched therein.
9. The semiconductor device as claimed in claim 8 , wherein the interface chip further includes a first counter circuit that updates a count value thereof based on the first read clock signal, and a second counter circuit that updates a count value thereof based on a signal generated by delaying the first read clock signal, the FIFO circuit includes a plurality of input circuits having input nodes commonly connected to the data path and a plurality of output circuits having input nodes each connected to an associated one of output nodes of the input circuits, the output circuits having output nodes being commonly connected, any one of the input circuits is activated based on the count value of the first counter circuit, and any one of the output circuits is activated based on the count value of the second counter circuit.
10. A semiconductor device comprising:
a plurality of core chips stacked to each other, each of the core chips including a memory cell array, a penetration electrode, and a FIFO circuit that latches read data that are read out from the memory cell array and sequentially outputs the read data latched therein; and
an interface chip that controls the core chips,
wherein the penetration electrodes of the core chips are commonly connected to each other so as to form a data path, the FIFO circuit includes a plurality of input circuits having input nodes to which each of the read data read out from the memory cell array is commonly supplied and a plurality of output circuits having input nodes each connected to an associated one of output nodes of the input circuits, the output circuits having output nodes being commonly connected to the penetration electrode, any one of the output circuits is activated based on a plurality of first read clock signals supplied from the interface chip, and the interface chip receives the read data through the data path, and
wherein any one of the input circuits is activated based on a plurality of second read clock signals generated in the corresponding core chip.
11. The semiconductor device as claimed in claim 10 , wherein the first read clock signals are successively generated in the interface chip by delaying a third read clock signal that is generated based on a read command supplied from outside, and the second read clock signals are successively generated by delaying the third read clock signal in the corresponding core chip.
12. A semiconductor device comprising:
a plurality of core chips stacked to each other, each of the core chips including a memory cell array, a data terminal, and an output circuit that outputs read data that is read out from the memory cell array to the data terminal; and
an interface chip that controls the core chips,
wherein the data terminals of the core chips are commonly connected to each other so as to form a data path common to the core chips, the output circuits are activated in response to a first read clock signal supplied from the interface chip, and the interface chip receives the read data through the data path in response to the first read clock signal.
13. The semiconductor device as claimed in claim 12 , wherein each of the data terminals includes a first penetration electrode that is provided through an associated one of the core chips, and the first penetration electrodes are arranged in the same planar position as viewed from a stacking direction and are short-circuited to each other.
14. The semiconductor device as claimed in claim 13 , wherein each of the core chips further includes an input circuit that latches the read data that is read out from the memory cell array, the output circuit outputs the read data latched by the input circuit to the first penetration electrode, and the input circuit latches the read data in response to a second read clock signal generated in the core chip.
15. The semiconductor device as claimed in claim 14 , wherein the interface chip includes a command decoder that generates a third read clock signal based on a read command supplied from outside, and a first delay circuit that generates the first read clock signal by delaying the third read clock signal.
16. The semiconductor device as claimed in claim 15 , wherein each of the core chips further includes a second delay circuit that generates the second read clock signal by delaying the third read clock signal.
17. The semiconductor device as claimed in claim 15 , wherein each of the core chips further includes a second penetration electrode, the second penetration electrodes of the core chips are commonly connected to each other so as to form a first signal path common to the core chips, and the interface chip commonly supplies the first read clock signal to the core chips through the first signal path.
18. The semiconductor device as claimed in claim 17 , wherein each of the core chips further includes a third penetration electrode, the third penetration electrodes of the core chips are commonly connected to each other so as to form a second signal path common to the core chips, the interface chip commonly supplies a chip address to the core chips through the second signal path, and each of the core chips causes the first read clock signal to be valid when the chip address supplied from the interface chip matches a unique chip address allocated to the corresponding core chip.
19. The semiconductor device as claimed in claim 18 , wherein each of the core chips further includes a fourth penetration electrode, the fourth penetration electrodes of the core chips are commonly connected to each other so as to form a third signal path common to the core chips, the interface chip commonly supplies the third read clock signal to the core chips through the third signal path, and each of the core chips causes the third read clock signal to be valid when the chip address supplied from the interface chip matches the unique chip address allocated to the corresponding core chip.
20. The semiconductor device as claimed in claim 14 , wherein each of the core chips includes a plurality of pairs of the output circuit and the input circuit, the read data read out from the memory cell array is commonly supplied to input nodes of the input circuits, each of output nodes of the input circuits is connected to an associated one of input nodes of the output circuits, output nodes of the output circuits are commonly connected to the first penetration electrode, any one of the input circuits is activated based on the second read clock signal, and any one of the output circuits is activated based on the first read clock signal.
21. The semiconductor device as claimed in claim 13 , wherein the interface chip further includes a FIFO circuit that latches the read data sequentially supplied through the data path and sequentially outputs the read data latched therein.
22. The semiconductor device as claimed in claim 21 , wherein the interface chip further includes a first counter circuit that updates a count value thereof based on the first read clock signal, and a second counter circuit that updates a count value thereof based on a signal generated by delaying the first read clock signal, the FIFO circuit includes a plurality of input circuits having input nodes commonly connected to the data path and a plurality of output circuits having input nodes each connected to an associated one of output nodes of the input circuits, the output circuits having output nodes being commonly connected, any one of the input circuits is activated based on the count value of the first counter circuit, and any one of the output circuits is activated based on the count value of the second counter circuit.