Non-volatile memory (NVM) and logic integration
A method of forming an NVM cell and a logic transistor uses a semiconductor substrate. A metal select gate of the NVM cell is formed over an NVM work function setting metal, the NVM work function setting metal is on a high-k dielectric, and a metal logic gate of a logic transistor is similarly formed over work function setting and high-k dielectric materials. The logic transistor is formed while portions of the metal select gate of the NVM cell are formed. The logic transistor is protected while the NVM cell is then formed including forming a charge storage region using nanocrystals and a metal control gate over a portion of the metal select gate and a portion of the charge storage region over the substrate. The charge storage region is etched to be aligned to the metal control gate.
1. A method of forming an NVM cell and a logic transistor using a semiconductor substrate, comprising:
in a non-volatile memory (NVM) region, forming over the semiconductor substrate a first high-k gate dielectric, an NVM work function setting metal, a metal select gate, and a first dielectric layer, wherein the work function setting layer is on the first high-k gate dielectric, the metal select gate is on the work function setting layer, a top surface of the first dielectric layer is substantially aligned with a top surface of the metal select gate, and the first dielectric layer has a first opening in which the work function setting layer and the metal select gate are present in the first opening;
in a logic region, forming over the semiconductor substrate a second high-k gate dielectric, a logic work function setting metal, a metal logic gate, a source and a drain in the semiconductor substrate, and a second dielectric layer, wherein the logic work function setting metal is on the second high-k gate dielectric, a top surface of the second dielectric layer is substantially aligned with a top surface of the metal logic gate, the second dielectric layer has a second opening in which the logic work function setting metal and the metal logic gate are present in the second opening, and the metal logic gate is on the logic work function setting metal;
removing the first dielectric layer in the NVM region while leaving the second dielectric layer in the logic region;
forming a charge storage layer comprising nanocrystals over the NVM region including over the metal select gate;
forming a metal layer over the charge storage layer;
patterning the metal layer to form a control gate; and
etching the charge storage layer to leave a remaining portion of the charge storage layer aligned to the control gate.
2. The method of claim 1 , wherein:
the forming the charge storage layer is further characterized by forming the charge storage layer over the second dielectric layer and the metal logic gate; and
the etching the charge storage layer is further characterized by removing the charge storage layer over the second dielectric layer and the metal logic gate.
3. The method of claim 2 , wherein:
the step of forming the metal layer is further characterized by forming the metal layer over the logic region; and
the step of patterning the metal layer is further characterized by removing the metal layer over the logic region.
4. The method of claim 3 , wherein the forming the first dielectric layer and forming the second dielectric layer are further characterized as forming the first dielectric and the second dielectric layers simultaneously of a same material.
5. The method of claim 1 , further comprising forming a first silicide region on the source and a second silicide region on the drain of the logic transistor prior to the forming of the second dielectric layer.
6. The method of claim 5 , further comprising:
forming a sidewall spacer around the metal logic gate prior to the forming the second dielectric layer.
7. The method of claim 6 , further comprising:
forming a liner around the metal logic gate prior to the forming the sidewall spacer.
8. The method of claim 7 , further comprising:
forming a hard mask over the NVM region and the logic region prior to the removing the first dielectric layer.
9. The method of claim 8 , further comprising removing the hard mask from over the NVM region while leaving the hard mask over the logic region prior to removing the first dielectric layer.
10. The method of claim 1 , wherein the forming the metal select gate and the forming the metal logic gate comprise a replacement gate process.
11. The method of claim 1 , wherein:
the forming the metal logic gate comprises forming a stack comprising a work function setting metal on the first high-k gate dielectric and a top metal over the work function setting metal.
12. The method of claim 1 , wherein:
the forming the metal logic gate comprises forming a stack having a first composition and the forming the metal select gate comprises forming a stack having a second composition wherein the first composition is different from the second composition.
13. The method of claim 1 , wherein the forming the charge storage layer comprises:
forming a base dielectric layer;
forming metal nanocrystals on the base dielectric layer; and
forming a fill dielectric layer around and over the metal nanocrystals.
14. A method of forming a non-volatile memory (NVM) cell and a logic transistor using a semiconductor substrate, comprising:
forming a first high-k gate dielectric and a second high-k gate dielectric over the semiconductor substrate;
forming a first work function setting metal on the first high-k gate dielectric and a second work function setting metal on the second high-k gate dielectric;
forming a first dummy gate over the first work function setting metal and a second dummy gate over the second work function setting metal;
forming a sidewall spacer around the second dummy gate;
forming first source/drains in the substrate adjacent to the second dummy gate;
forming a dielectric layer around the first dummy gate and the second dummy gate wherein a top surface of the dielectric layer is substantially aligned with a top surface of the first dummy gate and a top surface of the second dummy gate;
removing the first dummy gate and the second dummy gate;
replacing the first dummy gate with a select gate comprising a metal of a first type and the second dummy gate with a logic gate comprising a metal of the first type;
forming a hard mask over the logic gate and the first source/drains;
removing the dielectric layer from around the select gate while leaving the dielectric layer around the logic gate;
forming a charge storage layer comprising nanocrystals over the semiconductor substrate;
forming a metal layer over the charge storage layer;
patterning the metal layer to form a control gate over a portion of the select gate and a portion of the substrate and removing the metal layer from over the hard mask;
patterning the charge storage layer to leave a portion of the charge storage layer under the control gate and removing the charge storage layer over the hard mask; and
forming second source/drains in the substrate adjacent to the select gate and control gate.
15. The method of claim 14 , further comprising removing the hard mask.
16. The method of claim 15 further comprising siliciding the second source/drains prior to the removing the hard mask.
17. The method of claim 16 wherein the forming the charge storage layer is further characterized by the nanocrystals being metal.
18. The method of claim 14 , wherein the replacing the first dummy gate further comprises forming a metal of a second type on the metal of the first type.
19. A method, comprising:
forming a logic transistor having a metal logic gate over a logic work function setting metal, the logic work function setting metal on a high-k gate dielectric, a sidewall spacer around the metal logic gate, and silicided source/drains in a logic region of a semiconductor substrate and a metal select gate of a non-volatile memory (NVM) cell over an NVM work function setting metal, the NVM work function setting metal on a high-k dielectric and in an NVM region of the semiconductor substrate using a dielectric that is left around the metal logic gate and the metal select gate, wherein a top surface of the dielectric is substantially aligned to a top surface of the metal select gate and a top surface of the metal logic gate;
removing the dielectric from around the metal select gate;
forming a charge storage layer comprising nanocrystals over the logic region and the NVM region;
forming a metal layer over the logic region and the NVM region;
patterning the metal layer over the NVM region to form a metal control gate over a portion of the metal select gate and a portion of the substrate and removing the metal layer from the logic region;
etching the charge storage layer to leave the charge storage layer under and aligned with the metal control gate and to remove the charge storage layer over the logic region; and
forming source/drain regions in the substrate in the NVM region adjacent to the control gate and to the metal select gate.
20. The method of claim 19 further comprising:
forming a hard mask over the logic region prior to the removing the dielectric from around the metal select gate;
siliciding the source/drain regions in the substrate in the NVM region; and
removing the hard mask after the siliciding the source/drain regions in the substrate in the NVM region.