Workfunction metal stacks for a final metal gate

1. A method comprising:

forming an n-type area and a p-type area in a substrate;

forming a high-k dielectric layer over the n-type and p-type areas;

forming a pMOS workfunction metal stack layer on the high-k dielectric layer;

forming a hardmask layer on the pMOS workfunction metal stack layer on the n-type area;

removing the pMOS workfunction metal stack layer from the p-type area, exposing a portion of the high-k dielectric layer, wherein the portion extends over the p-type area;

forming an nMOS workfunction metal stack layer on the exposed portion of the high-k dielectric layer and on the hardmask layer; and

removing the nMOS workfunction metal stack layer from the hardmask layer.

2. The method according to claim 1 , further comprising:

removing the hardmask layer after removing the nMOS workfunction metal stack layer from the hardmask layer;

forming a polycrystalline silicon (poly-Si) or an amorphous silicon (a-Si) layer on the pMOS workfunction metal stack layer and on the nMOS workfunction metal stack layer; and

patterning the pMOS workfunction metal stack layer and the overlying poly-Si or a-Si layer to form a pMOS gate electrode, and patterning the nMOS workfunction metal stack layer and the overlying poly-Si or a-Si layer to form an nMOS gate electrode.

3. The method according to claim 2 , comprising forming the poly-Si or the a-Si to a thickness of 550 angstroms (A) to 650 A.

4. The method according to claim 1 , further comprising:

forming a shallow trench isolation (STI) region between the n-type area and the p-type area;

forming a channel silicon germanium (cSiGe) layer in the n-type area of the substrate; and

forming a high-k dielectric layer over the n-type and p-type areas prior to forming the pMOS workfunction metal stack layer.

5. The method according to claim 1 , comprising annealing the pMOS and nMOS workfunction metal stack layers at a temperature of 800° C. to 950° C. subsequent to removing the hardmask layer.

6. The method according to claim 1 , comprising forming the pMOS workfunction metal stack layer by:

forming a first layer of titanium nitride (TiN) to a thickness of 2 A to 10 A ;

forming a layer of aluminum (Al) to a thickness of 2 A to 8 A ; and

forming a second layer of TiN to a thickness of 15 A to 25 A .

7. The method according to claim 6 , comprising forming the nMOS workfunction metal stack layer by:

forming a layer of lanthanum (La) to a thickness of 2 A to 10 A ; and

forming a layer of TiN to a thickness of 15 A to 25 A.

8. The method according to claim 1 , comprising forming the hardmask layer by:

forming a layer of silicon nitride (SiN) over the p-type area and the n-type area; and removing the SiN from the p-type area by:

forming a resist over the n-type area; and

dry etching the SiN.

9. The method according to claim 1 , comprising forming the hardmask layer by:

forming a layer of silicon dioxide (SiO2) over the p-type area and the n-type area; and removing the SiO2from the p-type area by:

forming a resist over the n-type area; and

etching the SiO2 with hydrofluoric acid (HF).

10. The method according to claim 1 , comprising removing the nMOS workfunction metal stack layer from the n-type area by:

forming a resist on the p-type area; and

wet etching.

11. The method according to claim 1 , comprising removing the pMOS workfunction metal stack layer from the p-type area by:

forming a resist on the n-type area; and

wet etching.

12. A method comprising:

forming an n-type area and a p-type area in a substrate separated by a shallow trench isolation (STI) region;

forming a channel silicon germanium (cSiGe) layer in the n-type area;

forming a high-k dielectric layer over the p-type area, the STI region, and the cSiGe layer;

forming a pMOS workfunction metal stack layer on the high-k dielectric layer;

forming a hardmask layer on the pMOS workfunction metal stack layer;

removing a portion of the hardmask layer positioned over the p-type area, exposing a portion of the pMOS workfunction metal stack layer;

removing the exposed portion of the pMOS workfunction metal stack layer, exposing a portion of the high-k dielectric layer;

forming an nMOS workfunction metal stack layer on the exposed portion of the high-k dielectric layer and on a remaining portion of the hardmask layer;

removing a portion of the nMOS workfunction metal stack layer positioned on the remaining portion of the hardmask layer;

removing the remaining portion of the hardmask layer;

forming a polysilicon (poly-Si) or an amorphous silicon (a-Si) layer on a remaining portion of the pMOS workfunction metal stack layer and on a remaining portion of the nMOS workfunction metal stack layer; and

patterning the remaining portion of the nMOS workfunction metal stack layer and the overlying poly-Si or a-Si layer and the remaining portion of the pMOS workfunction metal stack layer and the overlying poly-Si or a-Si layer to form an nMOS gate electrode and a pMOS gate electrode, respectively.

13. The method according to claim 12 , comprising forming the pMOS workfunction by: forming a first layer of titanium nitride (TiN);

forming a layer of aluminum (Al); and

forming a second layer of TiN.

14. The method according to claim 12 , comprising forming the nMOS workfunction metal stack layer by:

forming a layer of lanthanum (La); and

forming a layer of TiN.

15. The method according to claim 12 , comprising forming the hardmask layer by forming a layer of silicon nitride (SiN) or silicon dioxide (SiO2).