Electrically tunable continuous-time circuit and method for compensating a polynomial voltage-dependent characteristic of capacitance
View Patent ↗A capacitance compensation circuit includes an input terminal, a plurality of switches coupled to the input terminal, a plurality of varactors coupled to the plurality of switches, and a plurality of blocking capacitors coupled between the plurality of switches and the plurality of varactors. The capacitance compensation circuit further includes a plurality of adjustable biasing circuits to precisely compensate for linear and parabolic voltage dependent components of an input or other capacitor. Two such circuits can be used with a single input terminal to compensate for both increasing and decreasing voltage dependent characteristics of a target capacitor.
1. A capacitance compensation circuit comprising:
an input terminal;
a plurality of switches coupled to the input terminal;
a plurality of varactors coupled to the plurality of switches; and
an adjustment circuit coupled to the plurality of varactors for separately minimizing second-order harmonic distortion and third-order harmonic distortion affecting a signal at the input terminal.
2. The capacitance compensation circuit of claim 1 further comprising a plurality of blocking capacitors coupled between the plurality of switches and the plurality of varactors.
3. The capacitance compensation circuit of claim 1 , wherein the plurality of switches comprises a plurality of devices inactivated by a switching voltage thereof exceeding a threshold voltage.
4. The capacitance compensation circuit of claim 1 , wherein the plurality of switches comprises a plurality of devices activated by a switching voltage thereof exceeding a threshold voltage.
5. The capacitance compensation circuit of claim 1 further comprising a plurality of bias levels coupled to a plurality of control terminals associated with the plurality of switches.
6. The capacitance compensation circuit of claim 5 , wherein the plurality of bias levels comprises a plurality of constant bias levels.
7. The capacitance compensation circuit of claim 2 , wherein the adjustment circuit comprises sing a plurality of bias devices coupled to the plurality of blocking capacitors.
8. The capacitance compensation circuit of claim 7 , wherein the adjustment circuit comprises an adjustable bias source coupled to the plurality of bias devices.
9. The capacitance compensation circuit of claim 1 , wherein the adjustment circuit comprises a plurality of adjustable bias levels coupled to the plurality of varactors.
10. The capacitance compensation circuit of claim 9 , wherein the adjustment circuit comprises an adjustable bias source to similarly adjust the capacitance of each varactor in the plurality of varactors.
11. The capacitance compensation circuit of claim 9 , wherein the adjustment circuit comprises an adjustable bias source to linearly adjust the capacitance of consecutive varactors in the plurality of varactors.
12. The capacitance compensation circuit of claim 1 , wherein the plurality of varactors comprises a plurality of MOS varactors.
13. The capacitance compensation circuit of claim 1 , wherein the plurality of varactors comprises a plurality of p-n junction varactors.
14. The capacitance compensation circuit of claim 1 , wherein each varactor in the plurality of varactors is coupled to a corresponding switch in the plurality of switches.
15. A method of compensating a capacitor at an input terminal comprising:
providing a plurality of switches coupled to the input terminal;
providing a plurality of blocking capacitors coupled to the plurality of switches;
providing a plurality of varactors coupled to the plurality of blocking capacitors; and
an adjustment circuit coupled to the plurality of varactors for separately minimizing second-order harmonic distortion and third-order harmonic distortion affecting a signal at the input terminal.
16. The method of claim 15 further comprising providing a threshold adjustment associated with a plurality of switch control nodes.
17. The method of claim 15 , wherein the adjustment circuit provides compensation for a linear variation of the input capacitance against the input terminal voltage via a constant bias adjustment coupled to a plurality of varactor terminals.
18. The method of claim 15 , wherein the adjustment circuit provides compensation for a quadratic variation of the input capacitance against the input terminal voltage via a linear bias adjustment coupled to a plurality of varactor terminals.
19. The method of claim 15 , wherein each varactor in the plurality of varactors is coupled to a corresponding blocking capacitor in the plurality of blocking capacitors.
20. The method of claim 15 , wherein each blocking capacitor in the plurality of blocking capacitors is coupled to a corresponding switch in the plurality of switches.
21. A capacitance compensation circuit comprising:
an input terminal;
a first plurality of varactors coupled to the input terminal;
a second plurality of varactors coupled to the first plurality of varactors at a plurality of intermediate nodes; and
an adjustment circuit coupled to the second plurality of varactors for separately minimizing second-order harmonic distortion and third-order harmonic distortion affecting a signal at the input terminal.
22. The capacitance compensation circuit of claim 21 , wherein the adjustment circuit comprises a bias adjustment circuit coupled to the plurality of intermediate nodes.
23. The capacitance compensation circuit of claim 21 , wherein the adjustment circuit comprises a bias adjustment circuit coupled to the second plurality of varactors.
24. The capacitance compensation circuit of claim 21 , wherein each varactor in the second plurality of varactors is coupled to a corresponding varactor in the first plurality of varactors at a corresponding intermediate node in the plurality of intermediate nodes.
25. A capacitance compensation circuit comprising:
an input terminal;
a first circuit portion including a first plurality of varactors coupled to the input terminal and a second plurality of varactors coupled to the first plurality of varactors at a first plurality of intermediate nodes;
a second circuit portion including a third plurality of varactors coupled to the input terminal and a fourth plurality of varactors coupled to the third plurality of varactors at a second plurality of intermediate nodes; and
adjustment circuits respectively coupled to the second and fourth plurality of varactors for separately minimizing second-order harmonic distortion and third-order harmonic distortion affecting a signal at the input terminal.
26. The capacitance compensation circuit of claim 25 , wherein the adjustment circuits respectively comprise a first bias adjustment circuit coupled to the first plurality of intermediate nodes, and a second bias adjustment circuit coupled to the second plurality of intermediate nodes.
27. The capacitance compensation circuit of claim 25 , wherein the adjustment circuits respectively comprise a first bias adjustment circuit coupled to the second plurality of varactors, and a second bias adjustment circuit coupled to the fourth plurality of varactors.
28. The capacitance compensation circuit of claim 25 , wherein each varactor in the second plurality of varactors is coupled to a corresponding varactor in the first plurality of varactors at a corresponding intermediate node in the first plurality of intermediate nodes.
29. The capacitance compensation circuit of claim 25 , wherein each varactor in the fourth plurality of varactors is coupled to a corresponding varactor in the third plurality of varactors at a corresponding intermediate node in the second plurality of intermediate nodes.