Methods and Apparatus for bump-on-trace Chip Packaging
Methods and apparatus for a solder mask trench used in a bump-on-trace (BOT) structure to form a semiconductor package are disclosed. A solder mask layer is formed on a trace and on a substrate. An opening of the solder mask layer, called a solder mask trench, is formed to expose the trace on the substrate. The solder mask trench has a width about a size of a diameter of a solder bump. A solder bump is landed directly on the exposed trace to connect a chip to the trace by an interconnect. With the formation of the solder mask trench, the trace exposed in the solder mask trench have a better grab force, which reduces the trace peeling failure for the semiconductor package. A plurality of solder mask trench rings may be formed in a package.
1 . A device comprising:
a substrate;
a trace on the substrate,
a solder mask layer on the substrate and on the trace, wherein the solder mask layer has a solder mask trench to expose the trace, and the solder mask trench has a width about a size of a diameter of a solder bump; and
a solder bump landed directly on the trace exposed by the solder mask trench wherein the solder bump is a part of an interconnect of a chip.
2 . The device of claim 1 , further comprising a chip connected to the interconnect.
3 . The device of claim 2 , further comprising an under-fill material filling a gap between the chip and the substrate.
4 . The device of claim 1 , wherein the substrate is made of a laminate or an organic material.
5 . The device of claim 1 , wherein the solder mask layer is about 30 to 40 microns in height.
6 . The device of claim 1 , wherein the trace comprises a material selected from a group consisting essentially of pure copper, aluminum copper, or alloys.
7 . The device of claim 1 , wherein the trace has a trace body that is of a substantially constant thickness.
8 . The device of claim 1 , wherein the interconnect is of a shape of a circle, an octagon, a rectangle, an oval, or a diamond.
9 . The device of claim 1 , wherein the interconnect comprises a post and the solder bump.
10 . The device of claim 1 , wherein the solder bump comprises a material selected from a group consisting essentially of tin, silver, lead-free tin, copper, or a combination thereof.
11 .- 17 . (canceled)
18 . A semiconductor package, comprising:
a substrate with a plurality of traces;
a solder mask layer on the substrate and the plurality of traces;
a trench in the solder mask layer to expose portions of the plurality of traces; and
at least one solder bump landed directly on at least one of the exposed plurality of traces, wherein the solder bump is a part of an interconnect of a chip.
19 . The package of claim 18 , wherein a pitch between two interconnects is less than about 140 um.
20 . The device of claim 1 , wherein the trace has a trace body that is of a substantially constant thickness.
21 . A device comprising:
a trace on a substrate,
a solder mask layer on the trace, wherein the solder mask layer has a solder mask trench to expose the trace, and the solder mask trench has a width about a size of a diameter of a connector; and
the connector landed on the trace exposed by the solder mask trench wherein the connector is a part of an interconnect of a chip.
22 . The device of claim 21 , further comprising a chip connected to the interconnect.
23 . The device of claim 21 , wherein the solder mask layer is about 30 to 40 microns in height.
24 . The device of claim 21 , wherein the trace comprises a material selected from a group consisting essentially of pure copper, aluminum copper, or alloys.
25 . The device of claim 21 , wherein the trace has a trace body that is of a substantially constant thickness.
26 . The device of claim 21 , wherein the interconnect is of a shape of a circle, an octagon, a rectangle, an oval, or a diamond.
27 . The device of claim 21 , wherein the interconnect comprises a post and a solder bump.