Apparatus and methods for a tamper resistant bus for secure lock bit transfer

1. In an integrated circuit, a tamper-resistant bus architecture for secure lock bit transfer, comprising:

a nonvolatile memory having an n-bit storage region for storing encoded lock bits;

a plurality of read access circuits coupled to the nonvolatile memory;

an n-bit tamper-resistant bus coupled to the read access circuits;

a decoder coupled to the tamper-resistant bus;

a k-bit decoded lock signal bus coupled to the decoder;

a controller coupled to the k-bit decoded lock signal bus;

an encode control bus coupling encode control signals from the controller to the decoder;

encode control circuitry disposed in the decoder and coupled to the encode control bus, the encode control circuitry having an output coupled to additional 1-bit lines of the tamper-resistant bus; and

encode control circuitry disposed in the read access circuits and coupled to additional 1-bit lines of the tamper-resistant bus, the encode control circuitry encoding the lock bits read by the read access circuits before placing them on the tamper-resistant bus.

2. The tamper-resistant bus architecture of claim 1 wherein:

a subset of the plurality of read access circuits include output inverters; and

the decoder has inverted inputs in bit positions corresponding to the ones of the read circuits that include output inverters.

3. The tamper-resistant bus architecture of claim 2 wherein the subset of the plurality of read access circuits include output inverters are alternating ones of the read access circuits.

4. The tamper-resistant bus architecture of claim 1 further including:

an encoder coupled between the read access circuits and the tamper-resistant bus; and

a flag signal bus coupled to the encoder for providing flag signals to the encoder.