IP Library Granted Patent US 8,952,311
Granted Patent B2
US 8,952,311 · App. 13/454,745 · Granted Feb 10, 2015

Imaging systems with column current mirror circuitry

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,952,311
App. No.
13/454,745
Granted
Feb 10, 2015
Kind
B2
Abstract

Electronic devices may include image sensors having image pixel arrays with image pixels arranged in pixel rows and pixel columns. Each pixel column may be coupled to an active and an inactive current supply circuit. Each active current supply circuit may form a portion of a current mirror circuit that includes a common current source and a common input transistor. Each active current supply circuit may include a mirror transistor for mirroring current that flows through the common input transistor and a permanently enabled enabling transistor for activating that mirror transistor. Mirrored current that flows through a particular active mirror transistor may be supplied to image pixels in the pixel column associated with that particular mirror transistor. Each inactive current supply circuit may include a mirror transistor coupled to the input transistor and a permanently disabled enabling transistor.

Claims (27)

1. An image sensor, comprising:

an array of image pixels arranged in pixel rows and pixel columns;

a plurality of active current supply circuits; and

a plurality of inactive current supply circuits, wherein at least one of the plurality of inactive current supply circuits and a corresponding one of the active current supply circuits are coupled to an associated one of the pixel columns, wherein the at least one of the plurality of inactive current supply circuits and the corresponding one of the active current supply circuits are coupled in parallel to the associated one of the pixel columns, wherein each image pixel in each pixel column comprises:

a photosensitive element; and

a source follower transistor having a gate terminal coupled to the photosensitive element, wherein the source follower transistors of the image pixels in each pixel column are configured to receive a bias current from the active current supply circuit that is coupled to that pixel column, wherein, in combination with additional circuitry on the image sensor, each of the active current supply circuits forms a corresponding current mirror circuit for providing the bias current, and wherein the current mirror circuit corresponding to each of the active current supply circuits comprises a feedback-assisted current mirror circuit.

2. The image sensor defined in claim 1 wherein the current mirror circuit corresponding to each of the active current supply circuits comprises a metal-oxide-semiconductor field-effect transistor current mirror circuit.

3. An image sensor, comprising:

an array of image pixels arranged in pixel rows and pixel columns;

a plurality of active current supply circuits; and

a plurality of inactive current supply circuits, wherein at least one of the plurality of inactive current supply circuits and a corresponding one of the active current supply circuits are coupled to an associated one of the pixel columns, wherein the at least one of the plurality of inactive current supply circuits and the corresponding one of the active current supply circuits are coupled in parallel to the associated one of the pixel columns, wherein each image pixel in each pixel column comprises:

a photosensitive element; and

a source follower transistor having a gate terminal coupled to the photosensitive element, wherein the source follower transistors of the image pixels in each pixel column are configured to receive a bias current from the active current supply circuit that is coupled to that pixel column, wherein, in combination with additional circuitry on the image sensor, each of the active current supply circuits forms a corresponding current mirror circuit for providing the bias current, wherein the additional circuitry comprises:

a current source; and

an input transistor coupled between the current source and the plurality of active current supply circuits.

4. The image sensor defined in claim 3 wherein each active current supply circuit comprises:

a mirror transistor having a gate terminal and a source/drain terminal, wherein the gate terminal is coupled to the source/drain terminal; and

an enabling transistor coupled to the mirror transistor, wherein the enabling transistor is configured to receive an enable signal that activates that active current supply circuit.

5. The image sensor defined in claim 4 wherein the input transistor comprises:

a gate terminal; and

a source/drain terminal coupled to the gate terminal, wherein the gate terminal of the input transistor is coupled to the gate terminal the mirror transistor of each active current supply circuit.

6. The image sensor defined in claim 5 wherein each inactive current supply circuit comprises:

a mirror transistor having a gate terminal and a source/drain terminal, wherein the gate terminal is coupled to the source/drain terminal; and

an enabling transistor coupled to the mirror transistor, wherein the enabling transistor is configured to inactivate that inactive current supply circuit.

7. The image sensor defined in claim 6 further comprising:

a plurality of conductive column lines, wherein each conductive column line in the plurality of conductive column lines is coupled to a respective pixel column; and

readout circuitry coupled to the conductive column lines for reading out image signals from the image pixels along the conductive column lines.

Assignments (5)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 18, 2014
From: APTINA IMAGING CORPORATION
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 034673/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 24, 2012
From: JOHNSON, RICHARD SCOTT
To: APTINA IMAGING CORPORATION
Reel/Frame 028099/0517 →