Programming and selectively erasing non-volatile storage

1. A non-volatile storage apparatus, comprising:

non-volatile storage elements; and

one or more managing circuits in communication with the non-volatile storage elements, the one or more managing circuits erasing the non-volatile storage elements, performing programming for said non-volatile storage elements, and selectively performing re-erasing of at least a subset of non-volatile storage elements that were supposed to remain erased without intentionally erasing programmed data.

2. A non-volatile storage apparatus according to claim 1 , wherein the one or more managing circuits selectively performing re-erasing of at least a subset of non-volatile storage elements that were supposed to remain erased comprises:

the one or more managing circuits identifying which non-volatile storage elements that should remain erased;

the one or more managing circuits testing whether said non-volatile storage elements that were supposed to remain erased appear to have been altered past a threshold; and

the one or more managing circuits performing one or more erase operations for non-volatile storage elements that should remain erased and appear to have been altered past said threshold.

3. A non-volatile storage apparatus according to claim 1 , wherein:

said non-volatile storage elements are NAND flash memory devices connected to a common word line.

4. A non-volatile storage apparatus according to claim 1 , wherein the one or more managing circuits performing programming for said non-volatile storage elements and the one or more managing circuits selectively performing re-erasing of at least said subset of non-volatile storage elements comprises:

the one or more managing circuits performing a first pass of a first multi-pass programming process for non-volatile storage elements connected to a first control line;

the one or more managing circuits performing a first pass of a second multi-pass programming process for non-volatile storage elements connected to a second control line;

after performing said first pass of said second multi-pass programming process, the one or more managing circuits selectively performing re-erasing of at least a subset of said non-volatile storage elements connected to said first control line that were supposed to remain erased;

the one or more managing circuits selectively performing re-erasing of at least a subset of said non-volatile storage elements connected to said second control line that were supposed to remain erased;

after selectively performing re-erasing of at least a subset of said non-volatile storage elements connected to said first control line, the one or more managing circuits performing a second pass of said first multi-pass programming process for at least some of said non-volatile storage elements connected to said first control line; and

the one or more managing circuits performing a second pass of said second multi-pass programming process for at least some of said non-volatile storage elements connected to said second control line.

5. A non-volatile storage apparatus according to claim 4 , wherein:

said first pass of said first multi-pass programming process is a coarse stage of said first multi-pass programming; and

said second pass of said first multi-pass programming process is a fine stage of said first multi-pass programming.

6. A non-volatile storage apparatus according to claim 4 , further comprising:

performing a first pass of a third multi-pass programming process on non-volatile storage elements connected to a third control line;

the one or more managing circuits selectively performing re-erasing of at least a subset of said non-volatile storage elements connected to said third control line that were supposed to remain erased; and

the one or more managing circuits performing a second pass of said third multi-pass programming process for said non-volatile storage elements connected to said third control line;

wherein the one or more managing circuits selectively performs re-erasing of at least a subset of said non-volatile storage elements connected to said second control line after performing said first pass of said third multi-pass programming process.

7. A non-volatile storage apparatus according to claim 1 , wherein the one or more managing circuits performing programming for said non-volatile storage elements and the one or more managing circuits selectively performing re-erasing of at least a subset of non-volatile storage elements comprises:

the one or more managing circuits performing a first pass of a first multi-pass programming process for said non-volatile storage elements connected to a first control line;

the one or more managing circuits performing a first pass of a second multi-pass programming process for said non-volatile storage elements connected to a second control line after performing said first pass of said first multi-pass programming process;

after performing said first pass of said second multi-pass programming process, the one or more managing circuits selectively performing re-erasing of at least a subset of said non-volatile storage elements connected to said first control line that were supposed to remain erased;

after selectively performing re-erasing of at least a subset of said non-volatile storage elements connected to said first control line, the one or more managing circuits selectively performing re-erasing of at least a subset of said non-volatile storage elements connected to said second control line that were supposed to remain erased;

after selectively performing re-erasing of at least a subset of said non-volatile storage elements connected to said second control line, the one or more managing circuits performing a second pass of said first multi-pass programming process for at least some of said non-volatile storage elements connected to said first control line; and

after performing said second pass of said first multi-pass programming process, the one or more managing circuits performing a second pass of said second multi-pass programming process for at least some of said non-volatile storage elements connected to said second control line.

8. A non-volatile storage apparatus according to claim 7 , wherein:

said first control line is adjacent to said second control line.

9. A non-volatile storage apparatus according to claim 1 , wherein:

said non-volatile storage elements are connected to a common word line;

the one or more managing circuits performing programming and selectively performing re-erasing on a word line basis; and

the one or more managing circuits erasing on a block basis.

10. A non-volatile storage apparatus according to claim 1 , further comprising:

said non-volatile storage elements include floating gates;

the one or more managing circuits receiving data to be stored by said set of non-volatile storage elements, said data indicating that some of said non-volatile storage elements are to be programmed and some of said non-volatile storage elements are to remain erased; and

the one or more managing circuits programming the non-volatile storage elements includes adding charge to floating gates indicated by said data to change state and not adding charge to floating gates indicated by said data to not change state.

11. A non-volatile storage apparatus according to claim 1 , wherein:

the one or more managing circuits selectively performing re-erasing comprises the one or more managing circuits selectively lowering threshold voltages of a subset of non-volatile storage elements, said subset of non-volatile storage elements are each part of different NAND strings.

12. A non-volatile storage apparatus according to claim 1 , wherein:

the non-volatile storage elements are on a common substrate region; and

the one or more managing circuits selectively performing re-erasing of at least a subset of non-volatile storage elements that were supposed to remain erased without intentionally erasing programmed data further comprises the one or more managing circuits performing one or more erase operations for at least a subset of non-volatile storage elements that were supposed to remain erased further comprises:

the one or more managing circuits boosting a first set of channel regions to a first voltage range for at least a subset of non-volatile elements that were supposed to remain erased without boosting a second set of channel regions to said first voltage range for a subset of non-volatile elements that were supposed to be programmed, said first set of channel regions and said second set of channel regions are part of the common substrate region wherein the one or more managing circuits apply said boosting by,

applying a boosting enabling voltage to at least a subset of non-volatile storage elements that were supposed to remain erased,

applying a boosting disabling voltage to said subset of non-volatile storage elements that were supposed to be programmed,

charging said common substrate region,

applying a voltage signal to an unselected common control line for coupling at least a subset of non-volatile storage elements that were supposed to remain erased and said subset of non-volatile storage elements that were supposed to be programmed to said unselected common control line,

applying a boosting signal beyond said voltage signal to said unselected common control line to boost said first set of channel regions, and

applying a common enabling voltage to at least a subset of non-volatile storage elements that were supposed to remain erased and said subset of non-volatile storage elements that were supposed to be programmed in order to lower threshold voltages of said at least a subset of non-volatile storage elements that were supposed to remain erased without intentionally lowering threshold voltages of said subset of non-volatile storage elements that were supposed to be programmed.

13. A non-volatile storage apparatus, comprising:

a set of non-volatile storage elements which are flash memory devices connected to a common word line; and

one or more managing circuits in communication with the set of non-volatile storage elements, the one or more managing circuits erasing the set of non-volatile storage elements;

the one or more managing circuits receiving data to be stored by said set of non-volatile storage elements, said data indicates that some of said non-volatile storage elements are to be programmed and some of said non-volatile storage elements are to remain erased;

the one or more managing circuits programming said data into said set of non-volatile storage elements; and selectively performing re-erasing of at least a first subset of non-volatile storage elements that were supposed to remain erased without intentionally erasing any non-volatile storage elements in a second subset storing properly programmed data by the one or more managing circuits:

applying non-negative boosting signals to unselected word lines for said set of non-volatile storage elements,

applying a boosting enabling voltage to bit lines for said first subset of non-volatile storage elements,

applying a boosting disabling voltage to bit lines for said second subset of non-volatile storage elements and

applying a non-negative voltage to said common word line.

14. A non-volatile storage apparatus according to claim 13 , wherein:

said set of non-volatile storage elements include floating gates;

the one or more managing circuits programming said data into said set of non-volatile storage elements includes the one or more managing circuits adding charge to floating gates indicated by said data to change state and the one or more managing circuits not adding charge to floating gates indicated by said data to not change state.

15. A non-volatile storage apparatus according to claim 13 , wherein:

said first subset of non-volatile storage elements are each part of different NAND strings.

16. A non-volatile storage apparatus according to claim 13 , wherein the one or more managing circuits programming said data into said set of non-volatile storage elements and selectively performing re-erasing comprises:

the one or more managing circuits performing a first pass of a first multi-pass programming process for non-volatile storage elements connected to a first control line;

the one or more managing circuits performing a first pass of a second multi-pass programming process for non-volatile storage elements connected to a second control line;

after performing said first pass of said second multi-pass programming process, the one or more managing circuits selectively performing re-erasing of at least a first subset of said non-volatile storage elements connected to said first control line that were supposed to remain erased;

the one or more managing circuits selectively performing re-erasing of at least a third subset of said non-volatile storage elements connected to said second control line that were supposed to remain erased;

after selectively performing re-erasing of at least said first subset of said non-volatile storage elements connected to said first control line, the one or more managing circuits performing a second pass of said first multi-pass programming process for non-volatile storage elements connected to said first control line; and

the one or more managing circuits performing a second pass of said second multi-pass programming process for non-volatile storage elements connected to said second control line.

17. A non-volatile storage apparatus according to claim 16 , wherein:

said first pass of said first multi-pass programming process is a coarse stage of said first multi-pass programming; and

said second pass of said first multi-pass programming process is a fine stage of said first multi-pass programming.

18. A non-volatile storage apparatus according to claim 16 , wherein:

said first pass of said first multi-pass programming process causes said non-volatile storage elements connected to said first control line to be in a first number of data states; and

said second pass of said first multi-pass programming process causes said non-volatile storage elements connected to said first control line to be in a second number of data states, said second number of data states is greater than said first number of data states.

19. A non-volatile storage apparatus, comprising:

non-volatile storage elements on a common substrate region; and

one or more managing circuits in communication with the plurality of non-volatile storage elements, the one or more managing circuits erasing non-volatile storage elements;

the one or more managing circuits performing programming for said non-volatile storage elements; and

one or more managing circuits selectively performing re-erasing of a subset of groups of non-volatile storage elements that were supposed to remain erased and which are connected to a common first set of control lines without intentionally erasing programmed data, each group includes multiple non-volatile storage elements in series and sharing a common channel area, by the one or more managing circuits performing one or more erase operations for the first subset of non-volatile storage elements that were supposed to remain erased comprising:

applying a boosting enabling voltage to a second set of control lines only for said subset of groups,

applying a boosting disabling voltage to a third set of control lines for groups of non-volatile storage elements not in said subset, and charging a common substrate for said groups, whether in or not in said subset, to a non-negative voltage, and

erasing one or more non-volatile storage elements in each group of said subset without intentionally erasing non-volatile storage elements in groups not in said subset by applying the non-negative voltage to said common first set of control lines.

20. The non-volatile storage apparatus according to claim 19 , wherein:

said groups of non-volatile storage elements are NAND strings; and

said common first set of control lines are word lines.

21. The non-volatile storage apparatus of claim 1 further comprising:

the non-volatile storage apparatus includes the non-volatile storage elements arranged in three-dimensions.

22. The non-volatile storage apparatus of claim 1 further comprising:

the non-volatile storage apparatus includes a three-dimensional memory array including the non-volatile storage elements.

23. The non-volatile storage apparatus of claim 1 further comprising:

the non-volatile storage elements use a dielectric layer for storing charge.