IP Library Granted Patent US 8,338,961
Granted Patent B2
US 8,338,961 · App. 13/456,968 · Granted Dec 25, 2012

Semiconductor chip with reinforcing through-silicon-vias

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Quick Facts
Patent No.
US 8,338,961
App. No.
13/456,968
Granted
Dec 25, 2012
Kind
B2
Abstract

A method of manufacturing includes connecting a first end of a first through-silicon-via to a first die seal proximate a first side of a first semiconductor chip. A second end of the first thu-silicon-via is connected to a second die seal proximate a second side of the first semiconductor chip opposite the first side.

Claims (29)

1. An apparatus, comprising:

a first semiconductor chip having a first side and a second and opposite side and including a first die seal proximate the first side and a second die seal proximate the second side; and

a first through-silicon-via having a first end connected to the first die seal and a second end connected to the second die seal.

2. The apparatus of claim 1 , wherein the first die seal is electrically connected to ground.

3. The apparatus of claim 1 , wherein the first semiconductor chip comprises an electrostatic discharge diode electrically connected to the first die seal.

4. The apparatus of claim 1 , comprising a third die seal proximate the first side and connected to the first end of the first through-silicon-via and a fourth die seal proximate the second side and connected to the second end of the first through-silicon-via.

5. The apparatus of claim 1 , comprising a third die seal proximate the first side, a fourth die seal proximate the second side, and a second through-silicon-via having a first end connected to the third die seal and a second end connected to the fourth die seal.

6. The apparatus of claim 5 , comprising a conductor member connected to adjacent surfaces of the first and second through-silicon-vias.

7. The apparatus of claim 1 , comprising a second semiconductor chip stacked on the first semiconductor chip.

8. The apparatus of claim 7 , wherein the first semiconductor chip comprises an interposer.

9. The apparatus of claim 1 , wherein the first semiconductor chip comprises a continuity circuit electrically connected to the first through-silicon-via.

10. The apparatus of claim 1 , comprising a gettering layer in the first semiconductor chip in contact with the first through-silicon-via.

11. An apparatus, comprising:

a circuit board;

a first semiconductor chip coupled to the circuit board and having a first side and a second and opposite side and including a first die seal proximate the first side and a second die seal proximate the second side; and

a first through-silicon-via having a first end connected to the first die seal and a second end connected to the second die seal.

12. The apparatus of claim 11 , wherein the circuit board comprises a semiconductor chip package substrate.

13. The apparatus of claim 11 , wherein the first semiconductor chip comprises an electrostatic discharge diode electrically connected to the first die seal.

14. The apparatus of claim 11 , comprising a third die seal proximate the first side and connected to the first end of the first through-silicon-via and a fourth die seal proximate the second side and connected to the second end of the first through-silicon-via.

15. The apparatus of claim 11 , comprising a third die seal proximate the first side, a fourth die seal proximate the second side, and a second through-silicon-via having a first end connected to the third die seal and a second end connected to the fourth die seal.

16. The apparatus of claim 15 , comprising a conductor member connected to adjacent surfaces of the first and second through-silicon-vias.

17. The apparatus of claim 11 , comprising a second semiconductor chip stacked on the first semiconductor chip.

18. The apparatus of claim 17 , wherein the first semiconductor chip comprises an interposer.

19. The apparatus of claim 11 , wherein the first semiconductor chip comprises a continuity circuit electrically connected to the first through-silicon-via.

20. The apparatus of claim 11 , comprising a gettering layer in the first semiconductor chip in contact with the first through-silicon-via.

21. An apparatus, comprising:

a first semiconductor chip having a first side and a second and opposite side and including a first die seal proximate the first side and a second die seal proximate the second side;

a first through-silicon-via having a first end connected to the first die seal and a second end connected to the second die seal; and

wherein the apparatus is embodied in instructions stored in a computer readable medium.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 22, 2025
From: REFAI-AHMED, GAMAL
To: ATI TECHNOLOGIES ULC
Reel/Frame 070907/0877 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 22, 2025
From: SU, MICHAEL Z.; BLACK, BRYAN
To: ADVANCED MICRO DEVICES, INC.
Reel/Frame 070908/0083 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 22, 2025
From: ATI TECHNOLOGIES ULC
To: ONESTA IP, LLC
Reel/Frame 070908/0290 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 18, 2024
From: ADVANCED MICRO DEVICES, INC.
To: ONESTA IP, LLC
Reel/Frame 069381/0951 →