Methods of channel stress engineering and structures formed thereby
Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a source/drain region in an NMOS portion of a substrate, wherein the source/drain region of the NMOS portion comprises at least one dislocation, and wherein a PMOS source/drain region in a PMOS portion of the substrate does not comprise a dislocation.
1. A structure comprising:
a source/drain region disposed in an NMOS portion of a substrate, wherein the source/drain region comprises at least one dislocation formation, the formation of the at least one dislocation is based upon a tensile stress in the NMOS portion, and wherein a PMOS source/drain region of a PMOS portion of the substrate does not comprise formation of a dislocation.
2. The structure of claim 1 wherein the at least one dislocation formation comprises an edge dislocation, and wherein the edge dislocation comprises a length of greater than about 20 nm.
3. The structure of claim 1 wherein the at least one dislocation formation is substantially adjacent to a channel region of the NMOS portion of the substrate.
4. The structure of claim 3 wherein the channel region comprises a strained channel capable of increased electron mobility.
5. The structure of claim 1 further comprising an NMOS gate disposed in the NMOS portion and a PMOS gate disposed in the PMOS portion, wherein at least one of the NMOS gate and the PMOS gate comprises a metal gate.
6. The structure of claim 1 wherein the substrate comprises a transistor structure comprising a PMOS portion and an NMOS portion.
7. The structure of claim 6 wherein the at least one dislocation formation is disposed in the substrate plane and in a plane perpendicular to a current flow of the transistor structure.
8. The structure of claim 1 wherein the structure is part of an integrated circuit.
9. A structure comprising:
a transistor substrate comprising an NMOS portion and a PMOS portion;
an NMOS gate disposed on the NMOS portion and a PMOS gate disposed on the PMOS portion, wherein a source/drain region disposed in the NMOS portion comprises at least one dislocation formation, the formation of the at least one dislocation is based upon a tensile stress in the NMOS portion, and wherein a source/drain region disposed in the PMOS portion of the substrate does not comprise formation of a dislocation; and
a strained channel region disposed in the NMOS portion, wherein the strained channel region is adjacent to the at least one dislocation.
10. The structure of claim 9 wherein the at least one dislocation formation comprises a first edge dislocation disposed in a first source/drain region of the NMOS portion of the substrate and a second edge dislocation disposed in a second source/drain region of the NMOS portion of the substrate.
11. The structure of claim 10 wherein the NMOS gate is disposed between the first source/drain region and the second source/drain region.
12. The structure of claim 10 wherein there is an angle between the first edge location and a top surface of the first source/drain, and wherein there is an angle between the second edge location and a top surface of second source/drain.
13. The structure of claim 10 wherein a length of the first edge location and a length of the second edge location are substantially the same.
14. The structure of claim 12 wherein the angle between the first edge location and the angle between the second edge location is between about 30 to about 60 degrees.
15. The structure of claim 10 wherein the first and second edge dislocations are capable of inducing strain in the strained channel.
16. The structure of claim 12 wherein the angles of the first and second edge dislocations are substantially the same.
17. The structure of claim 9 wherein the substrate comprises a CMOS transistor structure, wherein an NMOS transistor of the NMOS portion of the substrate comprises enhanced electron mobility due to the channel strain.
18. The structure of claim 9 wherein the structure is part of an integrated circuit.
19. A structure comprising:
a transistor substrate comprising an NMOS portion and a PMOS portion;
an NMOS gate disposed on the NMOS portion and a PMOS gate disposed on the PMOS portion, wherein a source/drain region disposed in the NMOS portion comprises at least one dislocation formation, the formation of the at least one dislocation is based upon a tensile stress in the NMOS portion, and wherein a source/drain region disposed in the PMOS portion of the substrate does not comprise formation of a dislocation; and
a strained channel region disposed in the NMOS portion, wherein the strained channel region is adjacent to the at least one dislocation formation, wherein the at least one dislocation formation comprises a first edge dislocation disposed in a first source/drain region of the NMOS portion of the substrate and a second edge dislocation disposed in a second source/drain region of the NMOS portion of the substrate, and wherein the first and second edge dislocations comprises a length of between about 20 nm and about 50 nm, and wherein an angle is disposed between a top surface of the first source/drain region of the NMOS portion and the first edge dislocation and wherein an angle is disposed between a top surface of the second source/drain region of the NMOS portion and the second edge dislocation.
20. The structure of claim 19 wherein the NMOS gate is disposed between the first source/drain region and the second source/drain region.
21. The structure of claim 19 wherein there is an angle between the first edge location and a top surface of the first source/drain, and wherein there is an angle between the second edge location and a top surface of second source/drain.
22. The structure of claim 19 wherein a length of the first edge location and a length of the second edge location are substantially the same.
23. The structure of claim 21 wherein the angle between the first edge location and the angle between the second edge location is between about 30 to about 60 degrees.
24. The structure of claim 19 wherein the first and second edge dislocations are capable of inducing strain in the strained channel.
25. The structure of claim 21 wherein the angles of the first and second edge dislocations are substantially the same.
26. The structure of claim 19 wherein the substrate comprises a CMOS transistor structure, wherein an NMOS transistor of the NMOS portion of the substrate comprises enhanced electron mobility due to the channel strain.
27. The structure of claim 19 wherein the structure is part of an integrated circuit.