IP Library Granted Patent US 8,357,975
Granted Patent B2
US 8,357,975 · App. 13/459,110 · Granted Jan 22, 2013

Semiconductor-on-insulator with back side connection

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Quick Facts
Patent No.
US 8,357,975
App. No.
13/459,110
Granted
Jan 22, 2013
Kind
B2
Abstract

Embodiments of the present invention provide for the removal of excess carriers from the body of active devices in semiconductor-on-insulator (SOI) structures. In one embodiment, a method of fabricating an integrated circuit is disclosed. In one step, an active device is formed in an active layer of a semiconductor-on-insulator wafer. In another step, substrate material is removed from a substrate layer disposed on a back side of the SOI wafer. In another step, an insulator material is removed from a back side of the SOI wafer to form an excavated insulator region. In another step, a conductive layer is deposited on the excavated insulator region. Depositing the conductive layer puts it in physical contact with a body of an active device in a first portion of the excavated insulator region. The conductive layer then couples the body to a contact in a second detached portion of the excavated insulator region.

Claims (34)

1. A semiconductor-on-insulator structure comprising:

an electrically conductive layer located in an excavated insulator region that is excavated on a bottom side of the structure;

an insulator layer being located above the electrically conductive layer, and partially vertically coextensive with the electrically conductive layer in the excavated insulator region;

an active layer being located above the insulator layer, the active layer comprising an active device with a body and a gate, wherein the gate is located above the body;

a handle wafer formed above the active layer; and

a body contact physically connecting the electrically conductive layer and the body, the body contact being located in a first portion of the excavated insulator region;

wherein the electrically conductive layer couples the body contact to a contact in the active layer, the contact being located in a second portion of the excavated insulator region, the second portion being detached from the first portion.

2. The semiconductor-on-insulator structure of claim 1 , wherein at least a portion of the electrically conductive layer is a lower resistivity metal.

3. The semiconductor-on-insulator structure of claim 2 wherein the metal is selected from the group consisting of aluminum and copper.

4. The semiconductor-on-insulator structure of claim 1 , further comprising: a circuit branch comprising the body contact and the contact;

wherein the circuit branch connects a source of the active device to the body of the active device.

5. The semiconductor-on-insulator structure of claim 1 , further comprising;

a circuit branch comprising the body contact and the contact;

wherein the circuit branch connects the gate of the active device to the body of the active device.

6. The semiconductor-on-insulator structure of claim 1 , further comprising:

a variable impedance circuit branch comprising the body contact and the contact;

wherein the variable impedance circuit branch is configured to have a high impedance when the active device is in an on state, and the variable impedance circuit branch is configured to have a low impedance when the active device is not in the on state.

7. The semiconductor-on-insulator structure of claim 6 , the variable impedance circuit branch further comprising:

a gate region of the active device;

wherein the variable impedance circuit branch latches the body to the gate voltage when the active device is in an off state.

8. The semiconductor-on-insulator structure of claim 1 , wherein:

the body contact is ohmic;

the contact is directly below a diode formed in the active layer; and

the diode is reversed biased when the active device is in an on state.

9. The semiconductor-on-insulator structure of claim 1 , wherein the body contact is a hot-carrier diode junction.

10. The semiconductor-on-insulator structure comprising:

an electrically conductive layer;

an insulator layer being at least partially vertically coextensive with the electrically conductive layer in an excavated insulator region that is excavated on a bottom side of the structure;

an active layer being located above the insulator layer, the active layer comprising an active device with a body and a gate, wherein the gate is located above the body;

a handle wafer formed above the active layer; and

a body contact physically connecting the electrically conductive layer and the body;

wherein the electrically conductive layer couples the body contact to a contact in the active layer.

11. The semiconductor-on-insulator structure of claim 10 , wherein at least a portion of the electrically conductive layer is a lower resistivity metal.

12. The semiconductor-on-insulator structure of claim 10 , wherein the metal is selected from the group consisting of aluminum and copper.

Assignments (8)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 23, 2016
From: QUALCOMM SWITCH CORP.
To: QUALCOMM INCORPORATED
Reel/Frame 038794/0663 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ERRONEOUS PATENT NUMBER 9029901 TO THE CORRECT PATENT NO. 9029201 AS PREVIOUSLY RECORDED ON REEL 036812 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE TERMINATION AND RELEASE OF GRANT OF SECURITY INTEREST AGAINST ALL PATENTS SET FORTH HEREIN. Recorded Oct 20, 2015
From: HSBC BANK AUSTRALIA LIMITED ABN 48 006 434 162
To: SILANNA SEMICONDUCTOR U.S.A., INC. (FORMERLY KNOWN AS IO SEMICONDUCTOR)
Reel/Frame 036907/0785 →
CHANGE OF NAME Recorded Oct 16, 2015
From: SILANNA SEMICONDUCTOR U.S.A., INC.
To: QUALCOMM SWITCH CORP.
Reel/Frame 036877/0140 →
TERMINATION AND RELEASE OF GRANT OF SECURITY INTEREST (PATENTS) Recorded Oct 7, 2015
From: HSBC BANK AUSTRALIA LIMITED ABN 48 006 434 162
To: SILANNA SEMICONDUCTOR U.S.A., INC. (FORMERLY KNOWN AS IO SEMICONDUCTOR)
Reel/Frame 036812/0429 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED ON REEL 035901 FRAME 0612. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNEE NAME SHOULD BE "IO SEMICONDUCTOR INCORPORATED". Recorded Jul 20, 2015
From: STUBER, MICHAEL A.; MOLIN, STUART B.; NYGAARD, PAUL A.
To: IO SEMICONDUCTOR INCORPORATED
Reel/Frame 036138/0868 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR NAME PREVIOUSLY RECORDED AT REEL: 033134 FRAME: 0338. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded Jul 15, 2015
From: IO SEMICONDUCTOR INCORPORATED
To: SILANNA SEMICONDUCTOR U.S.A., INC.
Reel/Frame 036109/0237 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 24, 2015
From: STUBER, MICHAEL A.; MOLIN, STUART B.; NYGAARD, PAUL A.
To: IO SEMICONDUCTOR INCORPORATED
Reel/Frame 035901/0612 →
CHANGE OF NAME Recorded Jun 11, 2014
From: IO SEMICONDUCTOR, INC.
To: SILANNA SEMICONDUCTOR U.S.A., INC.
Reel/Frame 033134/0338 →