RESISTANCE-SWITCHING MEMORY CELLS HAVING REDUCED METAL MIGRATION AND LOW CURRENT OPERATION AND METHODS OF FORMING THE SAME
In some aspects, a memory cell is provided that includes a steering element, a metal-insulator-metal (“MIM”) stack coupled in series with the steering element, and a conductor above the MIM stack. The MIM stack includes a resistance switching element and a top electrode disposed on the resistance switching element, and the top electrode includes a highly doped semiconductor material. The memory cell does not include a metal layer between the MIM stack and the conductor. Numerous other aspects are provided.
1 . A memory cell comprising:
a steering element;
a metal-insulator-metal (“MIM”) stack coupled in series with the steering element, wherein the MIM stack comprises a resistance switching element and a top electrode disposed on the resistance switching element, and the top electrode comprises a highly doped semiconductor material; and
a conductor disposed above the MIM stack,
wherein the memory cell does not include a metal layer disposed between the MIM stack and the conductor.
2 . The memory cell of claim 1 , wherein the steering element comprises a diode.
3 . The memory cell of claim 1 , wherein the steering element comprises a vertically oriented diode.
4 . The memory cell of claim 1 , wherein the steering element comprises a p-n or p-i-n diode.
5 . The memory cell of claim 1 , wherein the MIM stack is disposed above or below the steering element.
6 . The memory cell of claim 1 , wherein the resistance-switching material comprises a dielectric material.
7 . The memory cell of claim 6 , wherein the dielectric material comprises one or more of HfO x , ZrO x , La x O y , Ta x O y , SrTiO x , TiO x , SiO 2 , Al 2 O 3 , and Si 3 N 4 .
8 . The memory cell of claim 6 , wherein the dielectric material comprises a plurality of dielectric material layers.
9 . The memory cell of claim 6 , wherein dielectric material comprises a first dielectric material layer comprising one or more of one or more of HfO x , ZrO x , La x O y , Ta x O y , SrTiO x , and a second dielectric material layer comprising one or more of TiO x , SiO 2 , Al 2 O 3 , or Si 3 N 4 .
10 . The memory cell of claim 1 , wherein the top electrode comprises one of p+ silicon, p+ silicon-germanium, n+ silicon, and n+ silicon-germanium.
11 . The memory cell of claim 1 , wherein the MIM stack comprises a portion of the steering element.
12 . The memory cell of claim 11 , wherein
the steering element comprises a diode.
13 . The memory cell of claim 1 , wherein the MIM stack further comprises a bottom electrode disposed below the resistance-switching element, wherein the bottom electrode comprises a highly doped semiconductor material.
14 . The memory cell of claim 13 , wherein
the bottom electrode comprises one of p+ silicon, p+ silicon-germanium, n+ silicon, and n+ silicon-germanium.
15 . A monolithic three-dimensional memory array comprising:
a first memory level monolithically formed above a substrate, the first memory level comprising a plurality of memory cells, wherein each memory cell comprises:
a steering element;
a metal-insulator-metal (“MIM”) stack coupled in series with the steering element, wherein the MIM stack comprises a resistance switching element and a top electrode disposed on the resistance switching element, and the top electrode comprises a highly doped semiconductor material; and
a conductor disposed above the MIM stack,
wherein the memory cell does not include a metal layer disposed between the MIM stack and the conductor; and
a second memory level monolithically formed above the first memory level.
16 . The monolithic three-dimensional memory array of claim 15 , wherein the steering element comprises a diode.
17 . The monolithic three-dimensional memory array of claim 15 , wherein the steering element comprises a vertically oriented diode.
18 . The monolithic three-dimensional memory array of claim 15 , wherein the steering element comprises a p-n or p-i-n diode.
19 . The monolithic three-dimensional memory array of claim 15 , wherein each MIM stack is disposed above or below the steering element.
20 . The monolithic three-dimensional memory array of claim 15 , wherein the resistance-switching material comprises a dielectric material.
21 . The monolithic three-dimensional memory array of claim 20 , wherein the dielectric material comprises one or more of HfO x , ZrO x , La x O y , Ta x O y , SrTiO x , TiO x , SiO 2 , Al 2 O 3 , and Si 3 N 4 .
22 . The monolithic three-dimensional memory array of claim 20 , wherein the dielectric material comprises a plurality of dielectric material layers.
23 . The monolithic three-dimensional memory array of claim 20 , wherein dielectric material comprises a first dielectric material layer comprising one or more of one or more of HfO x , ZrO x , La x O y , Ta x O y , SrTiO x , and a second dielectric material layer comprising one or more of TiO x , SiO 2 , Al 2 O 3 , or Si 3 N 4 .
24 . The monolithic three-dimensional memory array of claim 15 , wherein the top electrode comprises one of p+ silicon, p+ silicon-germanium, n+ silicon, and n+ silicon-germanium.
25 . The monolithic three-dimensional memory array of claim 15 , wherein the MIM stack comprises a portion of the steering element.
26 . The monolithic three-dimensional memory array of claim 25 , wherein the steering element comprises a diode.
27 . The monolithic three-dimensional memory array of claim 15 , wherein the MIM stack further comprises a bottom electrode disposed below the resistance-switching element, wherein the bottom electrode comprises a highly doped semiconductor material.
28 . The monolithic three-dimensional memory array of claim 27 , wherein the bottom electrode comprises one of p+ silicon, p+ silicon-germanium, n+ silicon, and n+ silicon-germanium.