Methods of patterning small via pitch dimensions

1. An integrated circuit method, comprising:

providing a photomask that includes two main features for two via openings and further includes an optical proximity correction (OPC) feature linking the two main features;

forming a hard mask layer on a substrate, the hard mask layer including two trench openings;

forming a patterned resist layer over the hard mask layer using the photomask, wherein the patterned resist layer includes a peanut-shaped opening with two end portion aligned with the two trench openings of the hard mask layer, respectively; and

performing a first etch process to the substrate using the hard mask layer and the patterned resist layer as a combined etch mask.

2. The method of claim 1 , wherein

the two trench openings each have elongated shape oriented in a first direction;

the peanut-shaped opening of the patterned resist layer is oriented such that the two end portions are spaced away from each in a second direction different from the first direction.

3. The method of claim 2 , prior to the performing a first etch process to the substrate, further comprising forming spacers on side walls of the patterned resist layer and the hard mask layer by a procedure including deposition and etching.

4. The method of claim 3 , wherein the spacers fill in a necking portion of the peanut shaped opening, resulting in two separate openings defined by the patterned resist layer and the spaces.

5. The method of claim 2 , further comprising:

removing the patterned resist layer after the performing a first etching process to the substrate; and

thereafter, performing a second etch process to the substrate, forming two trenches and two vias in the substrate.

6. The method of claim 5 , further comprising:

filling the two trenches and the two vias with a conductive material; and

planarizing the conductive material and the substrate.

7. The method of claim 2 , wherein the second direction is orthogonal to the first direction.

8. The method of claim 1 , wherein the second direction is intersected with the first direction with an angle less than 90 degree.

9. The method of claim 1 , wherein the OPC feature includes a plurality of sub-resolution features.

10. The method of claim 1 , wherein the performing a first etch process to the substrate includes etching an interlayer dielectric (ILD) layer.

11. An integrated circuit method, comprising:

forming a patterned resist layer on a substrate having a peanut shaped opening;

forming a spacer on sidewalls of the peanut shaped opening of the patterned resist layer such that the spacer fills in a necking portion of the peanut shaped openings, resulting in two separate openings defined by the patterned resist layer and the spacer; and

performing an etch process to the substrate through the two separate openings using the patterned resist layer and the spacer as a combined etch mask.

12. The method of claim 11 , wherein the forming a patterned resist layer includes forming the patterned resist layer using a photomask that includes two features and an optical proximity correction (OPC) feature linking the two features.

13. The method of claim 12 , wherein the peanut-shaped opening of the patterned resist layer corresponds to an image of the two features and the OPC feature of the photomask by a lithography exposure process.

14. The method of claim 11 , wherein

the substrate includes a dielectric material layer formed on a semiconductor wafer; and

the performing an etch process includes performing the etch process to the dielectric material layer.

15. The method of claim 14 , further comprising forming, on the dielectric material layer, a hard mask having two trench openings before the forming a patterned resist layer on a substrate, wherein the peanut-shaped opening of the patterned resist layer has two end portions overlapped with the two trench openings of the hard mask, respectively.

16. The method of claim 15 , further comprising:

removing the patterned resist layer;

thereafter; performing another etch process to the dielectric material layer, forming two trenches and two vias in the dielectric material layer;

depositing a conductive material in the two trenches and two vias; and

performing a chemical mechanical polishing (CMP) process to remove excessive conductive material on the dielectric material layer.

17. The method of claim 11 , wherein the forming spacers on side walls of the patterned resist layer includes forming the spacers by a procedure including depositing a dielectric film and anisotropically etching the dielectric film.

18. An integrated circuit (IC) method, comprising:

receiving an IC design layout for an integrated circuit with via patterns;

adding an optical proximity correction (OPC) feature on the IC design layout to link at least two adjacent via patterns with the OPC feature, forming a modified IC design layout;

making a photomask using the modified IC design layout;

forming a dielectric material layer on a substrate;

forming, on the dielectric material layer, a hard mask having two openings that define trench lines;

forming a patterned resist layer on the hard mask using the photomask, wherein the patterned resist layer includes a peanut shaped opening with two end portions overlapped with the two openings; and

performing a first etch process to the dielectric material layer using the hard mask and the patterned resist layer as a combined etch mask.

19. The method of claim 18 , further comprising

removing the patterned resist layer;

thereafter performing a second etch process to the dielectric material layer through the two openings of the hard mask, resulting in the trench lines and vias in the dielectric material layer.