IP Library Granted Patent US 8,818,074
Granted Patent B2
US 8,818,074 · App. 13/466,506 · Granted Aug 26, 2014

Wafer edge inspection and metrology

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Quick Facts
Patent No.
US 8,818,074
App. No.
13/466,506
Granted
Aug 26, 2014
Kind
B2
Abstract

Some aspects of the present invention relate to a wafer inspection method. A plurality of images is acquired about an edge portion of a wafer. Each of the images comprises a pixel array having a first dimension and a second dimension. A composite image of compressed pixel arrays is generated by compressing each of the pixel arrays in the first dimension and concatenating the pixel arrays. The composite image is analyzed to identify a wafer feature, for example using a sinusoidal line fit.

Claims (17)

1. An edge inspection method comprising:

accessing a plurality of images of an edge portion of a substrate, each of the images comprising an array of pixels having a first dimension and a second dimension, each pixel of the array of pixels having a characteristic pixel value;

generating a composite image of compressed pixel arrays by compressing each of the pixel arrays in the first dimension based on an average of the characteristic pixel values of the pixel across the first dimension and concatenating the pixel arrays;

analyzing the composite image to identify a substrate feature; and

generating a composite image display that provides the composite image and an identification of the identified substrate feature with respect to the composite image.

2. The method of claim 1 , wherein the substrate feature comprises one or more resist edges.

3. The method of claim 1 , wherein the identification includes highlighted lines.

4. The method of claim 1 , further comprising obtaining and displaying metrics associated with the identified substrate feature.

5. The method of claim 1 , wherein the identified substrate feature is an edge.

6. The method of claim 1 , wherein the identified substrate feature is an origin of a bevel.

7. The method of claim 1 , further comprising identifying upper and lower edge bead removal tolerance lines.

8. The method of claim 1 , further comprising displaying a number of times an edge line is out of a predefined edge bead removal tolerance.

9. The method of claim 1 , further comprising identifying a resist center to substrate center offset.

10. The method of claim 1 , further comprising selecting a particular image frame acquisition location and displaying images associated with the location.

11. The method of claim 1 , further comprising displaying a separate window showing an uncompressed image.

12. The method of claim 1 , further comprising generating a scale.

13. The method of claim 1 , further comprising displaying a map of the substrate to demarcate location of an image frame.

Assignments (2)
CORRECTIVE ASSIGNMENT TO CORRECT THE THE NAMES OF THE CONVEYING PARTY BY ADDING AJAY PAI, TUAN D LE. PREVIOUSLY RECORDED AT REEL: 053117 FRAME: 0623. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jan 6, 2022
From: PAI, AJAY; LE, TUAN D; RUDOLPH TECHNOLOGIES, INC.
To: ONTO INNOVATION INC.
Reel/Frame 058571/0379 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 2, 2020
From: RUDOLPH TECHNOLOGIES, INC.
To: ONTO INNOVATION INC.
Reel/Frame 053117/0623 →