Nonvolatile memory device and method of manufacturing thereof
View Patent ↗A nonvolatile memory device and a method of manufacturing thereof are provided. The method includes forming a floating gate on a substrate, forming a dielectric layer to conform to a shape of the floating gate, forming a conductive layer to form a control gate on the substrate, the control gate covering the floating gate and the dielectric layer, forming a photoresist pattern on one side of the conductive layer, forming the control gate in the form of a spacer to surround sides of the floating gate, the forming of the control gate including performing an etch-back on the conductive layer until a portion of the dielectric layer on the floating gate is exposed, and forming a poly pad, to which a plurality of contact plugs are connected, on one side of the control gate, the forming of the poly pad including removing the photoresist pattern.
1. A method of manufacturing a nonvolatile memory device, the method comprising:
forming a floating gate on a substrate;
forming a dielectric layer to conform to a shape of the floating gate;
forming a conductive layer to form a control gate on the substrate, the control gate covering the floating gate and the dielectric layer;
forming a photoresist pattern on one side of the conductive layer;
forming the control gate in the form of a spacer to surround sides of the floating gate, the forming of the control gate comprising performing an etch-back on the conductive layer until a portion of the dielectric layer on the floating gate is exposed; and
forming a poly pad, to which a plurality of contact plugs are connected, on one side of the control gate, the forming of the poly pad comprising removing the photoresist pattern.
2. The method of claim 1 , wherein the control gate and the poly pad are connected to each other.
3. The method of claim 1 , wherein the poly pad is located at an end of an inclined portion of the control gate.
4. The method of claim 1 , wherein the poly pad includes a polysilicon peak that is formed over an inclined portion of the control gate.
5. A nonvolatile memory device, comprising:
a floating gate on a substrate;
a control gate having the form of a spacer, the control gate surrounding sides of the floating gate; and
a poly pad on one side of the control gate, a plurality of contact plugs being connected to the poly pad.
6. The nonvolatile memory device of claim 5 , further comprising:
a polysilicon peak between the control gate and the poly pad.
7. The nonvolatile memory device of claim 5 , wherein the control gate is connected to the floating gate and surrounds the floating gate.
8. The nonvolatile memory device of claim 5 , further comprising:
a silicide layer on the control gate, the silicide layer being configured to reduce a resistance of the control gate.
9. The nonvolatile memory device of claim 8 , further comprising:
a gate insulating layer on the substrate, the control gate being on the gate insulating layer.
10. The nonvolatile memory device of claim 9 , further comprising:
a tunnel insulating layer at a center of the gate insulating layer, the tunnel insulation layer having a thickness that is less than a thickness of the gate insulating layer.
11. The nonvolatile memory device of claim 10 , further comprising:
a hard mask on the floating gate.
12. The nonvolatile memory device of claim 11 , wherein a height of the control gate is:
less than or equal to a height of the hard mask and the floating gate combined; and greater than a height of the floating gate.
13. The nonvolatile memory device of claim 11 , further comprising:
a dielectric layer between the control gate and the floating gate.
14. The nonvolatile memory device of claim 13 , wherein the dielectric layer comprises:
a sidewall oxide layer contacting one side of the floating gate;
a high-voltage oxide layer; and
a sidewall nitride layer between the sidewall oxide layer and the high-voltage oxide layer.
15. The nonvolatile memory device of claim 13 , wherein the dielectric layer comprises an ONO stack including an oxide layer, a nitride layer, and an oxide layer.
16. The nonvolatile memory device of claim 13 , wherein the dielectric layer comprises a high-k oxide stack in which an aluminum oxide layer and a hafnium oxide layer are alternately deposited.
17. The nonvolatile memory device of claim 14 , wherein the high-voltage oxide layer:
is formed of the same material as the gate insulating layer; and
has a thickness that is less than the thickness of the gate insulating layer.
18. The nonvolatile memory device of claim 14 , further comprising:
a low-doped drain (LDD) spacer on an other side of the floating gate.
19. The nonvolatile memory device of claim 14 , further comprising:
a borderless contact (BLC) layer covering the floating gate, the control gate, and the dielectric layer.
20. The nonvolatile memory device of claim 19 , wherein:
the BLC layer, the high-voltage oxide layer, and the sidewall nitride layer contact one another;
the sidewall nitride layer contacts the hard mask; and
a side of the high-voltage oxide layer contacts the silicide layer and the control gate.
21. The nonvolatile memory device of claim 5 , further comprising:
a hard mask disposed above the floating gate;
a spacer surrounding sides of the control gate; and
a silicide layer disposed above the control gate between the hard mask and the spacer.
22. A nonvolatile memory device, comprising:
a plurality of floating gates on a substrate;
a plurality of control gates having the form of a spacer, each of the plurality of control gates surrounding sides of a corresponding floating gate of the plurality of floating gates; and
a poly pad that extends from one side of the plurality of control gates, a plurality of contact plugs being connected to the poly pad.
23. The nonvolatile memory device of claim 21 , further comprising:
a plurality of silicide layers, each silicide layer disposed above a control gate of the plurality of control gates, the plurality of silicide layers being configured to reduce a resistance of the plurality of control gates.