IP Library Granted Patent US 9,440,135
Granted Patent B2
US 9,440,135 · App. 13/482,045 · Granted Sep 13, 2016

Multilayer electronic structures with integral vias extending in in-plane direction

Inventor: Dror Hurwitz (Zhuhai, CN)
Assignee: Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd.
A63B69/3685A63B69/0059A63B69/36A63B69/3608A63B69/3676A63B2208/0204
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Quick Facts
Patent No.
US 9,440,135
App. No.
13/482,045
Granted
Sep 13, 2016
Kind
B2
Abstract

A multilayer electronic support structure comprising at least one pair of adjacent feature layers extending in an X-Y plane that are separated by a via layer; said via layer comprising a dielectric material that is sandwiched between the two adjacent feature layers and at least one one non-cylindrical via post that couples said pair of adjacent feature layers through the dielectric material in a Z direction perpendicular to the X-Y plane; wherein said at least one non-cylindrical via post is characterized by having a long dimension in the X-Y plane that is at least 3 times as long as a short dimension in the X-Y plane.

Claims (62)

1. A multilayer electronic support structure comprising at least a first feature layer extending in an X-Y plane and a second feature layer extending in an X-Y plane that is parallel to the first feature layer, said first and second feature layers being separated by a via layer; said feature layers comprising metal features surrounded by a dielectric material comprising a polymer matrix and said via layer comprising metal vias surrounded by the dielectric material wherein at least one non-cylindrical via post in the via layer conductively couples a first feature in the first feature layer with a second feature in the second feature layer, such that the first feature and the second feature are not in alignment in a Z direction perpendicular to the X-Y plane and do not overlap; wherein said at least one non-cylindrical via post is characterized by having a long dimension in the X-Y plane that is at least 3 times as long as a short dimension in the X-Y plane.

2. The multilayer electronic support structure of claim 1 comprising alternate layers of conductive vias and conductive features encapsulated by laminating in a dielectric, wherein a pair of conductive vias extend in the X-Y plane and enable conductive coupling between features having different positions in the X-Y plane.

3. The multilayer electronic support structure of claim 2 wherein the pair of conductive vias comprises an inductor.

4. The multilayer electronic support structure of claim 1 , wherein the at least non-cylindrical via post extending linearly within the X-Y plane by at least 500 microns.

5. The multilayer electronic support structure of claim 1 , wherein the at least one non-cylindrical via post extending linearly within the X-Y plane by several millimeters.

6. The multilayer electronic support structure of claim 1 , wherein the at least one non-cylindrical via post extending linearly within the X-Y plane has a Z dimension of at least 30 microns.

7. The multilayer electronic support structure of claim 1 , wherein the at least one non-cylindrical via post extending linearly within the X-Y plane has a Z dimension of at least 40 microns.

8. The multilayer electronic support structure of claim 1 , wherein the at least one non-cylindrical via post extending linearly within the X-Y plane has a Z dimension of at least 50 microns.

9. The multilayer electronic support structure of claim 1 , wherein the at least one non-cylindrical via post extending linearly within the X-Y plane has a width perpendicular to the Z dimension and to the linear extension of less than 50 microns.

10. The multilayer electronic support structure of claim 1 , wherein the at least one non-cylindrical via post in the via layer comprises a seed layer covered by a metal layer deposited thereover by electroplating.

11. The multilayer electronic support structure of claim 10 , wherein the seed layer comprises copper.

12. The multilayer electronic support structure of claim 10 , wherein the at least one non-cylindrical via post comprises copper.

13. The multilayer electronic support structure of claim 10 , wherein the at least one non-cylindrical via post is covered with a further metal seed layer.

14. The multilayer electronic support structure of claim 10 , wherein the seed layer further comprises a first deposited adhesive metal layer comprising at least one of the group comprising titanium, chromium, tantalum and tungsten.

15. The multilayer electronic support structure of claim 1 , wherein the at least one non-cylindrical via post in the via layer is a strip component having one dimension in the X-Y plane that is at least three times a perpendicular dimension in the X-Y plane.

16. The multilayer electronic support structure of claim 1 , wherein the at least one non-cylindrical via post in the via layer is a strip component that extends at least one millimeter.

17. The multilayer electronic support structure of claim 1 , wherein the at least one non-cylindrical via post in the via layer is a strip component that extends several millimeters.

18. The multilayer electronic support structure of claim 1 , wherein the at least one via layer is fabricated by a process comprising the steps of:

(a) obtaining a substrate including an underlying via layer that is treated to expose ends of vias in the underlying via layer;

(b) covering the substrate with a seed layer;

(c) depositing a layer of photo-resist over the seed layer;

(d) exposing and developing the photo-resist to form a negative pattern of features;

(e) depositing metal into the negative pattern to fabricate the first layer of features;

(f) stripping away photo-resist, leaving the first layer of features upstanding;

(g) applying a second layer of photoresist over the seed layer and the first layer of features;

(h) exposing and developing a pattern of vias including the at least one non-cylindrical via post having a long dimension in the X-Y plane that is at least 3 times as long as a short dimension in the X-Y plane in the second layer of photoresist;

(i) electroplating copper into the second pattern;

(j) stripping away the second layer of photoresist;

(k) removing the seed layer;

(l) laminating a dielectric material over the at least one non-cylindrical via post in the via layer;

(m) thinning the dielectric material to expose the metal of the at least one non-cylindrical via post;

(n) depositing a metal seed layer over the thinned dielectric material with the exposed metal non-cylindrical via post; and

(o) fabricating a second layer of features.

19. The multilayer electronic support structure of claim 18 , further characterized by at least one of:

(i) the seed layer comprises copper;

(ii) the metal via layer comprises copper;

(iii) the dielectric material comprises a polymer, and

(iv) the dielectric material comprises ceramic or glass reinforcements.

20. The multilayer electronic support structure of claim 18 , further characterized by at least one of:

(i) the dielectric layer comprises a polymer selected from the group comprising polyimide, epoxy, Bismaleimide, Triazine and blends thereof;

(ii) the dielectric layer comprises glass fibers, and

(iv) the dielectric layer comprises particle fillers.

21. The multilayer electronic support structure of claim 1 , wherein the at least one via layer is fabricated by a process comprising the steps of:

(i) obtaining a substrate including a first feature layer and having exposed copper;

(ii) covering the first feature layer with a seed layer;

(iii) depositing a metal layer over the seed layer;

(iv) depositing a layer of photo-resist over the seed layer;

(v) exposing a positive pattern of vias in the photoresist;

(vi) etching away the metal layer exposed;

(vii) stripping away the photo-resist, leave the at least one component in the via layer upstanding, and

(viii) laminating a dielectric material over the at least one component in the via layer.

22. The multilayer electronic support structure of claim 21 , comprising the further step: (ix) thinning the dielectric material to expose the metal.

23. The multilayer electronic support structure of claim 22 , comprising the further step: (x) depositing a second metal seed layer over the ground surface.

24. The multilayer electronic support structure of claim 22 , wherein at least one of the following limitations applies:

(a) the seed layer comprises copper;

(b) the metal layer comprises copper;

(c) the dielectric material comprises a polymer, and

(d) the dielectric material further comprises ceramic or glass reinforcements.

25. The multilayer electronic support structure of claim 22 , wherein at least one of the following limitations applies:

(e) the dielectric material comprises a polymer selected from the group comprising polyimide, epoxy, Bismaleimide, Triazine and blends thereof;

(f) the dielectric material comprises a polymer reinforced with glass fibers, and

(g) the dielectric material comprises a polymer and inorganic particle fillers.

Assignments (2)
CHANGE OF NAME Recorded May 9, 2019
From: ZHUHAI ADVANCED CHIP CARRIERS & ELECTRONIC SUBSTRATE SOLUTIONS TECHNOLOGIES CO. LTD.
To: ZHUHAI ACCESS SEMICONDUCTOR CO., LTD.
Reel/Frame 049152/0778 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 21, 2012
From: HURWITZ, DROR
To: ZHUHAI ADVANCED CHIP CARRIERS & ELECTRONIC SUBSTRATE SOLUTIONS TECHNOLOGIES CO. LTD.
Reel/Frame 028420/0428 →
Continuity (1)
Related Publication 20130319736A1 · Dec 5, 2013