Circuit technique to electrically characterize block mask shifts
View Patent ↗A physical test integrated circuit has a plurality of repeating circuit portions corresponding to an integrated circuit design. A first of the portions is fabricated with a nominal block mask location, and additional ones of the portions are deliberately fabricated with predetermined progressive increased offset of the block mask location from the nominal block mask location. For each of the portions, the difference in threshold voltage between a first field effect transistor and a second field effect transistor is determined. The predetermined progressive increased offset of the block mask location is in a direction from the first field effect transistor to the second field effect transistor. The block mask overlay tolerance is determined at a value of the progressive increased offset corresponding to an inflection of the difference in threshold voltage from a zero difference. A method for on-chip monitoring, and corresponding circuits, are also disclosed.
1. A method of characterizing block mask overlay tolerance of a static random access memory design, said method comprising the steps of:
fabricating a physical test integrated circuit having a plurality of repeating circuit portions comprising test static random access memory cells and corresponding to said static random access memory design, a first of said portions being fabricated with a nominal block mask location, additional ones of said portions being deliberately fabricated with predetermined progressive increased offset of said block mask location from said nominal block mask location, each of said test static random access memory cells in turn comprising a modified standard six field effect transistor static random access memory cell having a left-hand pass gate field effect transistor, a right-hand pass gate field effect transistor, a left-hand pull-up field effect transistor, a right-hand pull-up field effect transistor, a left-hand pull-down field effect transistor, and a right-hand pull-down field effect transistor, each of said test static random access memory cells being modified in that:
said left-hand pass gate field effect transistor and said right-hand pass gate field effect transistor are shorted;
said left-hand pull-up field effect transistor and said right-hand pull-up field effect transistor are shorted; and
an input voltage node is provided by electrically connecting gates of said left-hand pull-up field effect transistor, said right-hand pull-up field effect transistor, said left-hand pull-down field effect transistor, and said right-hand pull-down field effect transistor;
for each of said portions, determining a difference in threshold voltage between one of said left-hand pull-down field effect transistor and said right-hand pull-down field effect transistor and another one of said left-hand pull-down field effect transistor and said right-hand pull-down field effect transistor, wherein said predetermined progressive increased offset of said block mask location is in a direction from said one of said left-hand pull-down field effect transistor and said right-hand pull-down field effect transistor to said another one of said left-hand pull-down field effect transistor and said right-hand pull-down field effect transistor;
determining said block mask overlay tolerance at a value of said progressive increased offset corresponding to an inflection of said difference in threshold voltage from a zero difference, and
wherein, in said step of determining said difference in threshold voltage between said one of said left-hand pull-down field effect transistor and said right-hand pull-down field effect transistor and said another one of said left-hand pull-down field effect transistor and said right-hand pull-down field effect transistor, said direction from said one of said left-hand pull-down field effect transistor and said right-hand pull-down field effect transistor to said another one of said left-hand pull-down field effect transistor and said right-hand pull-down field effect transistor is parallel to an x-axis.
2. The method of claim 1 , wherein said fabricating comprises fabricating said plurality of repeating circuit portions in a column with a plurality of rows, said first of said portions being fabricated in a first of said rows, said additional ones of said portions being fabricated in additional ones of said rows, said predetermined progressive increased offset of said block mask location from said nominal block mask location comprising a uniform increase for each successive one of said rows.