Granted Patent B2

US 8,729,874 · App. 13/490,163 · Granted May 20, 2014

Abstract

Claims (28)

1. A low power voltage regulator comprising:

a first diode-connected transistor of a first polarity type in series with a second diode-connected transistor of a second polarity type coupled between an output node and ground;

a first bias current having a value for biasing the first and second diode-connected transistors in a sub-threshold mode of operation: and

a buffer amplifier comprising an input transistor having a gate forming an input of the buffer amplifier coupled to the output node, a drain, and a source forming an output of the buffer amplifier for providing the regulated output voltage, a feedback transistor having a gate coupled to the drain of the input transistor, a source for coupling to a power supply voltage, and a drain coupled to the source of the input transistor, a second bias current coupled to the drain of the input transistor, and a third bias current coupled to the source of the input transistor.

2. The low power voltage regulator of claim 1 wherein the first diode-connected transistor comprises a P-channel transistor.

3. The low power voltage regulator of claim 1 wherein the second diode-connected transistor comprises an N-channel transistor.

4. The low power voltage regulator of claim 1 wherein the first bias current is generated by a bandgap circuit.

5. A method of providing a regulated output voltage comprising:

providing a first diode-connected transistor of a first polarity type in series with a second diode-connected transistor of a second polarity type coupled between an output node and ground; and

biasing with a first bias current the first and second diode-connected transistors in a sub-threshold mode of operation for low power operation; and

buffering the regulated output voltage with a buffer amplifier comprising an input transistor having a gate forming an input of the buffer amplifier coupled to the output node, a drain, and a source forming an output of the buffer amplifier for providing the regulated output voltage, a feedback transistor having a gate coupled to the drain of the input transistor, a source for coupling to a power supply voltage, and a drain coupled to the source of the input transistor, a second bias current coupled to the drain of the input transistor, and a third bias current coupled to the source of the input transistor.

6. The method of claim 5 wherein the first diode-connected transistor comprises a P-channel transistor.

7. The method of claim 5 wherein the second diode-connected transistor comprises An N-channel transistor.

8. A low power voltage regulator comprising:

a first diode-connected transistor of a first polarity type in series with a second diode-connected transistor of a second polarity type coupled between an output node and ground;

a first bias current having a value for biasing the first and second diode-connected transistors in a sub-threshold mode of operation;

a third transistor coupled between the first bias current and the first and second diode-connected transistors; and

a buffer amplifier coupled to the third transistor, the buffer amplifier comprising:

an input transistor having a gate forming an input of the buffer amplifier, a drain, and a source forming an output of the buffer amplifier for providing the regulated output voltage;

a feedback transistor having a gate coupled to the drain of the input transistor, a source for coupling to a power supply voltage, and a drain coupled to the source of the input ransistor;

a second bias current coupled to the drain of the input transistor; and

a third bias current coupled to the source of the input transistor.

9. The low power voltage regulator of claim 8 wherein the third bias current is greater than the second bias current.

10. The low power voltage regulator of claim 8 wherein the input transistor comprises an N-channel transistor.

11. The low power voltage regulator of claim 8 wherein the feedback transistor comprises a P-channel transistor.

12. The low power voltage regulator of claim 8 wherein the first diode-connected transistor comprises a P-channel transistor.

13. The low power voltage regulator of claim 8 wherein the second diode-connected transistor comprises an N-channel transistor.

14. The low power voltage regulator of claim 8 wherein the first bias current is generated by a bandgap circuit.

Assignments (9)