Fast carry lookahead circuits
View Patent ↗A fast lookahead carry adder includes adder logic and lookahead carry-path logic coupled to the adder logic. The carry path logic has a main carry path, a carry entrance path and a carry exit path, the carry entrance path separate from the carry exit path.
1. A carry lookahead circuit for a fast carry adder comprising:
a carry-in signal node;
first, second, and third carry-input signal nodes; first, second, and third propagate signal nodes;
first, second, and third local carry-out signal nodes;
a carry-out signal node;
a first buffer having an input and an output, the input coupled to the carry-in signal node and the output coupled to the first local carry-out signal node;
a first multiplexer having a first data input coupled to the first carry-input signal node, a second data input coupled to the output of the first buffer, a control input coupled to the first propagate signal node, and an output coupled to the second local carry-out signal node;
a second multiplexer having a first data input coupled to the second carry-input signal node, a second data input coupled to the first carry-input signal node, a control input coupled to the second propagate signal node, and an output;
a third multiplexer having a first data input coupled to the third carry-input signal node, a second data input coupled to the output of the second multiplexer, and a control input coupled to the third propagate input signal node, and an output;
an AND gate having a first input coupled to the first propagate signal node, a second input coupled to the second propagate signal node, a third input coupled to the third propagate signal node′ and an output;
a fourth multiplexer having a first data input coupled to the output of the third multiplexer, a second data input coupled to the carry-in signal node, a control input coupled to the output of the AND gate, and an output coupled to the carry-out signal node;
a fifth multiplexer having a first data input coupled to the second carry-input signal node, a second data input coupled to the output of the first multiplexer, a control input coupled to the second propagate signal node, and an output coupled to the third local carry-out signal node; and
wherein the output of the first buffer is coupled to the first local carry-out signal node through a second buffer, the output of the first multiplexer is coupled to the second local carry-out signal node through a third buffer, the output of the fifth multiplexer is coupled to the third local carry-out signal node through a fourth buffer, and
wherein the first buffer is smaller than each of the second, third, and fourth buffers.
2. The carry lookahead circuit of claim 1 , wherein the output of the fourth multiplexer is coupled to the carry-out signal node through a buffer.
3. The carry lookahead circuit of claim 1 , wherein the output of the third multiplexer is coupled to the first data input of the fourth multiplexer through a buffer.