Method for verifying mask pattern of semiconductor device
View Patent ↗Provided is a method for verifying a pattern of a semiconductor device. In the method, a designed layout of target patterns is provided, and transferring the designed layout on a wafer to form wafer patterns. Wafer patterns image contour is obtain. The image contour for wafer patterns on the designed layout are matched, After edge differences between the designed layout and the wafer patterns image contour are extracted, a checking layout for detecting wafer pattern defects is obtain by adding the edge differences on the designed layout. Defects on the checking layout is identified to verify the patterns in view of processes before fabrication of a photomask.
1. A method for verifying a mask pattern of a semiconductor device, the method comprising:
providing a designed layout of target patterns;
forming wafer patterns on a wafer by transferring the designed layout on the wafer;
obtaining an image contour of the wafer patterns from the wafer;
matching the image contour of the wafer patterns on the designed layout;
extracting edge differences data between edge points of the designed layout and the image contour of the wafer patterns;
generating checking layout for detecting wafer pattern defects by including the edge differences data on a data of the designed layout; and
checking defects on the checking layout.
2. The method of claim 1 , wherein the designed layout comprises one of an original layout for the target pattern or an optical proximity corrected layout of the original layout.
3. The method for claim 1 , wherein the step of transferring the designed layout on a wafer further comprising:
fabricating a photomask using the designed layout for the target pattern; and
forming wafer patterns on the wafer using the fabricated photomask.
4. The method of claim 1 , wherein the step of obtaining the image contour is performed with the aid of a scanning electron microscope.
5. The method of claim 1 , wherein the step of extracting edge differences further comprising:
comparing an edge point of a pattern of the designed layout with an edge point of a wafer pattern of the image contour;
converting differences between the edge points of the wafer pattern of the image contour and the edge point on a pattern designed layout into a GDS data; and
storing the GDS data.
6. The method of claim 1 , wherein the step of obtaining a checking layout converting a critical dimension of a pattern of the designed layout into a critical dimension of a pattern of the checking layout by adding the edge difference in an edge point of the pattern of the designed layout.
7. The method of claim 1 , wherein the step of identifying defects further comprising:
dividing the checking layout into a line pattern region and a space region; and
detecting of the defects in the line pattern region and in the space region.
8. The method of claim 7 , wherein the step of detecting the line pattern region further comprising:
providing a reference critical dimension value of the line pattern; and
determining whether a critical dimension of a pattern in the checking layout deviates from the reference critical dimension value.
9. The method of claim 7 , wherein the step of detecting the defects in the space region comprising: providing a reference dispacing value between line patterns; and
determining whether a dispacing between line patterns in the checking layout deviates from the reference dispacing value.
10. The method of claim 2 , further comprising performing another optical proximity correction by feed back the detected defects on the designed layout.
11. A method for verifying a mask pattern of a semiconductor device, the method comprising:
providing a designed layout of target patterns;
forming wafer patterns on a wafer by transferring the designed layout on the wafer;
obtaining an image contour of the wafer patterns from the wafer;
matching the image contour of the wafer patterns on the designed layout;
extracting edge differences data between edge points of the designed layout and the image contour of the wafer patterns;
generating a checking layout for detecting wafer pattern defects by including the edge differences data in an edge point of the pattern of the designed layout to convert a critical dimension of a pattern of the designed layout into a critical dimension of a pattern of the checking layout;
providing a reference critical dimension value for a pattern; and
determining whether the critical dimension of the pattern of the checking layout deviates from the reference critical dimension value.
12. The method of claim 11 , wherein the designed layout comprises one of an original layout for the target pattern or an optical proximity corrected layout of the original layout.
13. The method of claim 11 , wherein the step of extracting edge differences further comprising:
comparing an edge point of a pattern of the designed layout with an edge point of a wafer pattern of the image contour;
converting differences between the edge points of the wafer patterns of the image contour and the edge point on a pattern designed layout into a GDS data; and
storing the GDS data.
14. The method of claim 12 , further comprising performing another optical proximity correction by feed back the detected defect to the designed layout.
15. A method for verifying a mask pattern of a semiconductor device, the method comprising:
providing a designed layout of target patterns;
forming wafer patterns on a wafer by transferring the designed layout on the wafer;
obtaining an image contour of the wafer patterns from the wafer;
matching the image contour of the wafer patterns on the designed layout;
extracting edge differences data between the edge points of the designed layout and the image contour of the wafer patterns;
generating a checking layout for detecting wafer pattern defects by including the edge differences data in an edge point of the pattern of the designed layout to convert a critical dimension of a pattern of the designed layout into a critical dimension of a pattern of the checking layout;
providing a reference dispacing value for a dispacing between patterns; and
determining whether the dispacing between the pattern of the checking layout deviates from the reference dispacing value.
16. The method of claim 15 , wherein the designed layout comprises one of an original layout for the target pattern or an optical proximity corrected layout of the original layout.
17. The method of claim 15 , wherein the extracting edge differences further comprising:
comparing an edge point of a pattern of the designed layout with an edge point of a wafer pattern of the image contour;
converting differences between the edge points of the wafer pattern of the image contour and the edge point on a pattern designed layout into a GDS data; and
storing the GDS data.
18. The method of claim 16 , further comprising performing another optical proximity correction by feed back the detected defects to the designed layout.