IP Library Granted Patent US 8,704,555
Granted Patent B2
US 8,704,555 · App. 13/511,321 · Granted Apr 22, 2014

Integrated circuit comprising reference voltage generation circuitry and electronic device

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Quick Facts
Patent No.
US 8,704,555
App. No.
13/511,321
Filed
May 22, 2012
Granted
Apr 22, 2014
Kind
B2
Examiner
KIM, JUNG H
Art Unit
2842
USPC
327/530
Abstract

An integrated circuit comprises reference voltage generation circuitry for providing a reference voltage for use within a transmission of electrical signals. The reference voltage generation circuitry comprises a reference voltage node operably coupled via a plurality of resistance elements to a plurality of signal nodes such that the reference voltage node assumes as the reference voltage an average of the voltage values of the signal nodes to which it is coupled.

Claims (36)

1. An integrated circuit comprising reference voltage generation circuitry for providing a reference voltage for use within a transmission of electrical signals, the reference voltage generation circuitry comprising a reference voltage node coupled via a plurality of resistance elements to a plurality of signal nodes such that the reference voltage node assumes as the reference voltage an average of voltage values of the signal nodes to which it is coupled, wherein the reference voltage generation circuitry further comprises a data transfer monitor coupled to the reference voltage node and arranged to monitor signals being transmitted, and determine therefrom whether any correction is required to be applied to the reference voltage based at least partly on the signals being transmitted, and wherein the data transfer monitor is arranged to count a number of states of signals transmitted, and compare the count to a threshold value to determine whether to apply a correction to the reference voltage.

2. An integrated circuit comprising reference voltage generation circuitry for providing a reference voltage for use within a transmission of electrical signals, the reference voltage generation circuitry comprising a reference voltage node coupled via a plurality of resistance elements to a plurality of signal nodes such that the reference voltage node assumes as the reference voltage an average of voltage values of the signal nodes to which it is coupled, wherein the reference voltage generation circuitry further comprises pull-up/pull-down comparator circuitry coupled to the reference voltage node, the pull-up/pull-down comparator circuitry comprising:

a first comparator circuit arranged to compare the reference voltage to a first reference threshold, and if the reference voltage is above the first reference threshold to pull-down the reference voltage; and

a second comparator circuit arranged to compare the reference voltage to a second reference threshold, and if the reference voltage is below the second reference threshold to pull-up the reference voltage.

3. The integrated circuit of claim 1 wherein at least a number of the plurality of signal nodes are arranged to form a part of a high speed signal path for conveying dynamic signals, each dynamic signal comprising a voltage swing about the reference voltage.

4. The integrated circuit of claim 3 wherein the number of signal nodes form at least part of a data and/or address bus.

5. The integrated circuit of claim 4 wherein the number of signal nodes form at least a part of a double data rate (DDR) interface.

6. The integrated circuit of claim 1 wherein the reference voltage generation circuitry forms part of one of the group consisting of: a signal processing integrated circuit and a memory integrated circuit.

7. An electronic device comprising reference voltage generation circuitry for providing a reference voltage for use within a transmission of electrical signals, the reference voltage generation circuitry comprising:

a reference voltage node coupled via resistors to a plurality of signal nodes such that the reference voltage node assumes as the reference voltage an average of the voltage values of the signal nodes to which it is coupled; and

pull-up/pull-down comparator circuitry coupled to the reference voltage node, the pull-up/pull-down comparator circuitry comprising:

a first comparator circuit arranged to compare the reference voltage to a first reference threshold, and if the reference voltage is above the first reference threshold to pull-down the reference voltage; and

a second comparator circuit arranged to compare the reference voltage to a second reference threshold, and if the reference voltage is below the second reference threshold to pull-up the reference voltage.

8. The electronic device of claim 7 wherein the reference voltage generation circuitry further comprises a capacitance coupled between the reference voltage node and a ground plane.

9. The electronic device of claim 8 wherein the data transfer monitor is arranged to count a number of states of signals transmitted, and compare the count to a threshold value to determine whether to apply a correction to the reference voltage.

10. The electronic device of claim 8 wherein the reference voltage generation circuitry further comprises a data transfer monitor coupled to the reference voltage node and arranged to monitor signals being transmitted, and determine therefrom whether any correction is required to be applied to the reference voltage based at least partly on the signals being transmitted.

11. An integrated circuit comprising:

a plurality of signal nodes, each signal node of the plurality of signal nodes comprising a single signal line; and

a reference voltage generation circuit for providing a reference voltage for the plurality of signal nodes, the reference voltage generation circuit comprising:

a reference voltage node;

a plurality of resistance elements, wherein each resistance element of the plurality of resistance elements is coupled between the reference voltage node and an associated signal node of the plurality of signal nodes, such that the reference voltage is an average of a plurality of voltage values of the plurality of signal nodes; and

pull-up/pull-down comparator circuitry coupled to the reference voltage node, the pull-up/pull-down comparator circuitry comprising:

a first comparator circuit arranged to compare the reference voltage to a first reference threshold, and if the reference voltage is above the first reference threshold to lower the reference voltage; and

a second comparator circuit arranged to compare the reference voltage to a second reference threshold, and if the reference voltage is below the second reference threshold to raise the reference voltage.

12. The integrated circuit of claim 11 wherein the reference voltage generation circuitry further comprises a capacitance coupled between the reference voltage node and a ground plane.

13. An integrated circuit comprising:

a plurality of signal nodes, each signal node of the plurality of signal nodes comprising a single signal line; and

a reference voltage generation circuit for providing a reference voltage for the plurality of signal nodes, the reference voltage generation circuit comprising:

a reference voltage node;

a plurality of resistance elements, wherein each resistance element of the plurality of resistance elements is coupled between the reference voltage node and an associated signal node of the plurality of signal nodes, such that the reference voltage is an average of a plurality of voltage values of the plurality of signal nodes; and

a data transfer monitor coupled to the reference voltage node and arranged to monitor signals being transmitted over the plurality of signal nodes, and to determine whether to apply a correction to the reference voltage based on the signals being transmitted, wherein the data transfer monitor is arranged to count a number of states of signals transmitted, and compare the count to a threshold value to determine whether to apply the correction to the reference voltage.

14. The integrated circuit of claim 13 wherein the reference voltage generation circuitry further comprises pull-up/pull-down comparator circuitry coupled to the reference voltage node, the pull-up/pull-down comparator circuitry comprising:

a first comparator circuit arranged to compare the reference voltage to a first reference threshold, and if the reference voltage is above the first reference threshold to lower the reference voltage; and

a second comparator circuit arranged to compare the reference voltage to a second reference threshold, and if the reference voltage is below the second reference threshold to raise the reference voltage.

15. The integrated circuit of claim 11 wherein a number of signal nodes of the plurality of signal nodes are arranged to form a high speed signal path for conveying a plurality of dynamic signals, each dynamic signal comprising a voltage swing about the reference voltage.

16. The integrated circuit of claim 15 wherein the number of signal nodes form a part of a data and an address bus.

Assignments (14)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 17, 2018
From: NXP USA, INC.
To: VLSI TECHNOLOGY LLC
Reel/Frame 045084/0184 →
MERGER Recorded Jan 3, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041144/0363 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →