Managing interrupts
View Patent ↗A process for managing interrupts, which may be performed using electronic circuitry, includes: receiving interrupts bound for a processing device, where the interrupts are received from hardware devices that are configured to communicate with the processing device; generating data containing information corresponding to the interrupts; and sending the data to the processing device.
1. A method performed by electronic circuitry, comprising:
receiving interrupts bound for a processing device, the interrupts being received from different hardware devices that are configured to communicate with the processing device;
generating data containing information corresponding to the interrupts, wherein generating comprises aggregating the interrupts in a single data packet; and
sending the data packet to the processing device.
2. The method of claim 1 , wherein the data packet is a first data packet; and
wherein the method further comprises:
generating a second data packet, the second data packet identifying the electronic circuitry; and
sending the second data packet to the processing device following the first data packet.
3. The method of claim 2 , wherein the electronic circuitry comprises a first aggregator; and
wherein the second data packet comprises a signature unique to the first aggregator.
4. The method of claim 1 , wherein at least some interrupts are received via a dedicated transmission path, and wherein at least some interrupts are multiplexed on a same transmission path.
5. The method of claim 1 , wherein the data packet contains an address that corresponds to the processing device.
6. Electronic circuitry comprising:
an input interface for receiving interrupts bound for a processing device, the interrupts being received from different hardware devices that are configured to communicate with the processing device;
a data generator for generating data containing information corresponding to the interrupts, wherein generating comprises aggregating the interrupts in a single data packet; and
an output interface for sending the data packet to the processing device.
7. The electronic circuitry of claim 6 , wherein the data packet is a first data packet;
wherein the data generator is configured to generate a second data packet, the second data packet identifying the electronic circuitry; and
wherein the second data packet is sent over the output interface to the processing device following the first data packet.
8. The electronic circuitry of claim 7 , wherein the electronic circuitry comprises a first aggregator; and
wherein the second data packet comprises a signature unique to the first aggregator.
9. The electronic circuitry of claim 8 , wherein at least some interrupts are received via a dedicated transmission path between corresponding hardware and the electronic circuitry, and wherein at least some interrupts are multiplexed on a same transmission path.
10. The electronic circuitry of claim 6 , wherein the data packet contains an address that corresponds to the processing device.
11. A system comprising:
a processing device;
one or more first dedicated lines for transmitting first interrupts having a first latency;
one or more second dedicated lines for transmitting second interrupts having a second latency that is different from the first latency, interrupts on the second lines being multiplexed for transmission; and
circuitry to receive the first interrupts and the second interrupts, to generate a data packet corresponding to the first interrupts and the second interrupts, and to send the data packet to the processing device, wherein generating comprises aggregating the first and second interrupts in the data packet, the data packet being a single data packet.
12. The system of claim 11 , wherein the data packet is a first data packet and the circuitry is configured to a send second data packet to the processing device, the second data packet being sent after the first data packet, the second data packet identifying the circuitry.
13. The system of claim 12 , wherein the circuitry comprises a first aggregator; and
wherein the second data packet comprises a signature unique to the first aggregator.
14. The system of claim 11 , wherein the data packet contains an address that corresponds to the processing device.
15. The system of claim 11 , further comprising a PCI Express bus to interconnect the circuitry and the processing device, the data packet being sent over the PCI Express bus.
16. The system of claim 15 , wherein the system further comprises a second processing device, wherein the circuitry is configured to send the data packet to the second processing device.
17. The system of claim 16 , wherein the first and second processing devices are root complexes.
18. The system of claim 16 , wherein the data packet is a first data packet and the circuitry is configured to a send second data packet to the second processing device, the second data packet being sent after the first data packet, the second data packet identifying the circuitry.