Copper feature design for warpage control of substrates
View Patent ↗An approach is provided in which a laminate substrate includes top layers, bottom layers, and a core layer. The top layers are positioned between the core layer and a top surface metallurgy (TSM) layer and include at least one top conductive layer. The bottom layers are positioned between the core layer and a bottom surface metallurgy (BSM) layer and include at least one bottom conductive layer that includes a material void pattern that is based upon the top conductive layer and reduces warpage of the laminate substrate.
1. An apparatus comprising:
a laminate substrate, the laminate substrate comprising:
a core layer comprising a glass reinforced epoxy;
one or more top layers positioned between the core layer and a top surface metallurgy (TSM) layer, wherein at least one of the top layers is a top conductive layer comprising a wiring pattern that electrically connects a plurality of first nodes on the top conductive layer; and
one or more bottom layers positioned between the core layer and a bottom surface metallurgy (BSM) layer, wherein at least one of the bottom layers is a bottom conductive layer, the bottom conductive layer further comprising:
a material void pattern that corresponds to the wiring pattern included on the top conductive layer, wherein the material void pattern reduces warpage of the laminate substrate.
2. The apparatus of claim 1 wherein the bottom conductive layer includes copper that electrically connects a plurality of second nodes included on the bottom conductive layer, and wherein the material void pattern fails to change the electrical connectivity between the plurality of second nodes.
3. The apparatus of claim 1 wherein the top conductive layer and the bottom conductive layer are paired and are equidistant from the core layer.
4. The apparatus of claim 3 wherein the laminate substrate further comprises:
a plurality of top conductive layers that includes the top conductive layer;
a plurality of bottom conductive layers that includes the bottom conductive layer, wherein each of the plurality of bottom conductive layers are paired to one of the plurality of top conductive layers, and wherein each of the plurality of bottom conductive layers includes one or more different material void patterns that are based upon one or more different wiring patterns included in their corresponding paired top conductive layer.
5. The apparatus of claim 1 wherein the material void pattern is a channel pattern that forms one or more non-contiguous shapes.
6. The apparatus of claim 5 wherein the channel pattern includes straight lines that forms the one or more non-contiguous shapes.
7. The apparatus of claim 5 wherein the channel pattern includes irregular curved lines.
8. The apparatus of claim 1 further comprising:
a flip chip die attached to the TSM layer; and
a plurality of connection contact pads attached to the BSM layer.