IP Library Granted Patent US 9,137,905
Granted Patent B2
US 9,137,905 · App. 13/531,948 · Granted Sep 15, 2015

Alignment between layers of multilayer electronic support structures

Inventors: Dror Hurwitz (Guangdong, CN); Simon Chan (Zhuhai, CN)
Assignee: Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd.
H05K3/4679H01L21/4857H01L23/49822H01L2924/0002H05K3/4647H05K2203/025
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Quick Facts
Patent No.
US 9,137,905
App. No.
13/531,948
Granted
Sep 15, 2015
Kind
B2
Abstract

A process for alignment a subsequent layer over a previous layer comprising metal features or vias encapsulated in dielectric material comprising the steps of: thinning and planarizing the dielectric material to create a smooth surface of dielectric material and coplanar exposed ends of the via posts; imaging the smooth surface; discerning the position of the end of at least one feature, and using the position of the end of at least one via feature as a registration mark for aligning the subsequent layer.

Claims (21)

1. A process for aligning an upper layer comprising upper metal features over a lower layer of a substrate comprising a dielectric material with a plurality of via posts extending therethrough, comprising the steps of:

a) thinning and planarizing the dielectric material and an upper end of each via post to create a smooth surface comprising the dielectric material and coplanar exposed upper end of each via post;

b) imaging the smooth surface;

c) discerning the position of the upper end of one of the plurality of via posts, and

d) using the position of the upper end of one of the plurality of via posts as a registration mark for said aligning said upper layer over said lower layer.

2. The process of claim 1 , wherein the lower layer via posts and upper layer metal features are fabricated by electroplating into photoresist.

3. The process of claim 1 wherein said imaging comprises computerized optical analysis of the image obtained to determine edges of the upper end of the at least one via post.

4. The process of claim 1 further comprising step a1) of depositing a seed layer over the smooth surface such that step c) of discerning the position of the upper end of one of the plurality of via posts comprises discerning the position of the upper end of one of the plurality of via posts through the seed layer.

5. The process of claim 1 further comprising step a1) of depositing an adhesion/barrier layer over the thinned dielectric layer and then depositing a seed layer such that step c) of discerning the position of the upper end of one of the plurality of via posts comprises discerning the position of the upper end of one of the plurality of via posts through the seed layer and the photoresist layer.

6. The process of claim 1 further comprising step a1) of depositing an adhesion/barrier layer over the thinned dielectric layer and then depositing a seed layer followed by laying a photoresist layer over the seed layer such that step c) of discerning the position of the upper end of one of the plurality of via posts comprises discerning the position of the upper end of one of the plurality of via posts through the adhesion/barrier layer, the seed layer and the photoresist layer.

7. The process of claim 4 wherein the seed layer is characterized by having a thickness of up to 3 microns.

8. The process of claim 4 wherein the seed layer is deposited by physical vapor deposition (PVD) or an electroless deposition process and comprises at least one metal selected from the group comprising Ni, Au, Cu and Pd.

9. The process of claim 5 , wherein the adhesion/barrier layer is characterized by a thickness between 0.04 to 0.2 microns and is deposited by a physical vapor deposition process (PVD) and comprises at least one metal selected from the group comprising Ti, Ta, W, Ni, Cr, Pt, Al and Cu.

10. The process of claim 1 wherein step a) comprises at least one of the techniques selected from the group comprising mechanical grinding, mechanical polishing and chemical Mechanical Polishing (CMP).

11. The process of claim 1 wherein a plurality of upper ends of via posts are imaged and a pattern for the upper layer is written by a laser, using upper ends of via posts from the plurality of via posts to make adjustments to correct the position of the laser whilst exposing and developing the pattern.

12. The process of claim 11 being automated by a control computer.

13. The process of claim 1 wherein a plurality of upper ends of via posts are imaged and the position of the plurality of upper ends of via posts are used to position a photomask.

14. The process of claim 1 wherein alignment of better than +−10 microns is attainable.

15. The process of claim 1 wherein alignment of better than +−3 microns is attainable.

16. The process of claim 1 , wherein at least one upper end of a via post used to align said upper layer over said lower layer has a cross section that includes at least one straight edge.

17. The process of claim 1 , wherein at least one upper end of a via post used to align said upper layer over said lower layer has a cross section that includes at least two perpendicular straight edges.

Assignments (2)
CHANGE OF NAME Recorded May 20, 2019
From: ZHUHAI ADVANCED CHIP CARRIERS & ELECTRONIC SUBSTRATE SOLUTIONS TECHNOLOGIES CO. LTD.
To: ZHUHAI ACCESS SEMICONDUCTOR CO., LTD.
Reel/Frame 049234/0641 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 25, 2012
From: HURWITZ, DROR; CHAN, SIMON
To: ZHUHAI ADVANCED CHIP CARRIERS & ELECTRONIC SUBSTRATE SOLUTIONS TECHNOLOGIES CO. LTD.
Reel/Frame 028436/0742 →
Continuity (1)
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